Frequency Generator & Integrated Buffers for Celeron & PII/III GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1

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1 Integrated Circuit Systems, Inc. ICS92-2 Frequency Generator & Integrated Buffers for Celeron & PII/III Recommended Application: 8/8E and Solano type chipset Output Features: V, up to.mhz. - up to.mhz. - 2x PCI MHz fixed. - - Features: Up to.mhz frequency support Support power management through PD#. Spread spectrum for EMI control (±.2%) center spread. Uses external.8mhz crystal FS pins for frequency select Key Specifications: CPU Output Jitter: <2ps IOAPIC Output Jitter: < 8MHz, V66, PCI Output Jitter: < Ref Output Jitter. <ps CPU Output Skew: <7ps PCI Output Skew: < V66 Output Skew <7ps For group skew timing, please refer to the Group Timing Relationship Table. VDDREF X X2 GNDREF GNDV66 V66- V66- V66-2 VDDV66 VDDPCI *FS/PCICLK *FS/PCICLK PCICLK2 GNDPCI PCICLK PCICLK PCICLK VDDPCI PCICLK6 PCICLK7 GNDPCI PD# SCLK SDATA VDDSDR SDRAM SDRAM GNDSDR Block Diagram Pin Configuration 6-Pin mil SSOP These pins will have to 2X drive strength * 2K ohm pull-up to VDD on indicated inputs PLL ICS REF/FS* VDDLAPIC IOAPIC VDDLCPU CPUCLK CPUCLK GNDLCPU GNDSDR SDRAM SDRAM SDRAM2 VDDSDR SDRAM SDRAM SDRAM GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND8 2MHz/FS2* 8MHz/FS* VDD8 VDDSDR SDRAM8 SDRAM9 GNDSDR 8MHz / 2 2MHz X X2 XTAL OSC REF PLL Spread Spectrum CPU DIVDER 2 CPUCLK [:] SDRAM DIVDER 2 SDRAM [:] FS[:] PD# Control Logic IOAPIC DIVDER SDRAM_F IOAPIC SDATA SCLK Config. Reg. PCI DIVDER 8 PCICLK [7:] V66 DIVDER V66 [2:] 92-2 Rev A // PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

2 ICS92-2 General Description The ICS92-2 is a single chip clock solution for desktop designs using the 8/8E and Solano style chipset It provides all necessary clock signals for such a system Spread spectrum may be enabled through I 2 C programming Spread spectrum typically reduces system EMI by 8dB to db This simplifies EMI qualification without resorting to board design iterations or costly shielding The ICS92-2 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations Serial programming I 2 C interface allows changing functions, stop clock programming and frequency selection Pin Configuration PIN NUMBER PIN NAME TYPE DESCRIPTION, 9,, 8, 2, 2,, 7, VDD PWR.V power supply 2 X IN Crystal input, has internal load cap (pf) and feedback resistor from X2 X2 OUT Crystal output, nominally.8mhz. Has internal load cap (pf),,, 2, 28, 29, 6, GND PWR Ground pins for.v supply, 9 8, 7, 6 V66 [2:] OUT.V Fixed 66MHz clock outputs for HUB PCICLK OUT.V PCI clock outputs, with Synchronous CPUCLKS FS I N Logic input frequency select bit. Input latched at power on. 2 PCICLK IN.V PCI clock outputs, with Synchronous CPUCLKS FS I N Logic input frequency select bit. Input latched at power on. 2, 9, 7, 6,, PCICLK [7:2] OUT.V PCI clock outputs, with Synchronous CPUCLKS 22 PD# IN Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than ms. 2 SCLK IN 2 Clock input of I C input 2 SDATA IN 2 Data input for I C serial input. 8MHz OUT.V Fixed 8MHz clock output for USB FS I N Logic input frequency select bit. Input latched at power on. FS2 I N Logic input frequency select bit. Input latched at power on. 2MHz OUT.V fixed 2MHz output 8 SDRAM_ F OUT.V free running MHz SDRAM not affected by I 2 C 8, 7,,, 2,, 9,, SDRAM [:] OUT.V output running MHz. All SDRAM outputs can be turned off through I 2 C,, 27, 26 GNDL PWR Ground for 2.V power supply for CPU & APIC, 2 CPUCLK [:] O UT 2.V Host bus clock output. Output frequency derived from FS pins., VDDL PWR 2.V power suypply for CPU, IOAPIC IOAPIC O UT 2.V clock outputs running at 6.67MHz. FS I N Logic input frequency select bit. Input latched at power on. 6 REF O UT.V,.8MHz reference clock output. 2

3 ICS92-2 Frequency Selection FS FS FS2 FS FS CPU MHz SDRAM MHz V66 MHz PCI MHz IOAPIC MHz Clock Enable Configuration PD# CPUCLK SDRAM IOAPIC 66MHz PCICLK REF, 8MHz Osc VCOs LOW LOW LOW LOW LOW LOW OFF OFF ON ON ON ON ON ON ON ON

4 ICS92-2 Byte : Functionality and frequency select register (Default=) ( = enable, = disable) (2, 7:) Description (2,7:) CPUCLK SDRAM V66 IOAPIC PCICLK MHz MHz MHz MHz Frequency is selected by hardware select, latched inputs - Frequency is selected by 2,6: - Normal - Spread spectrum enable ±.2% Center Spread - Running - Tristate all outputs Notes: Default at power-up will be for latched logic inputs to define frequency, as displayed by 2 The I 2 C readback for 2, 7: indicate the revision code PWD Note

5 ICS92-2 Byte : Control Register ( = enable, = disable) B it Pin# PWD Description 7 - X FS# 6 - X FS# - X FS2# 2MHz - (Reserved) 2 8MHz - (Reserved) 8 SDRAM_ F Byte 2: Control Register ( = enable, = disable) B it Pin# PWD Description 7 9 SDRAM7 6 SDRAM6 2 SDRAM SDRAM SDRAM 2 6 SDRAM2 7 SDRAM 8 SDRAM Byte : Control Register ( = enable, = disable) B it Pin# PWD Description 7 2 PCICLK7 6 9 PCICLK6 7 PCICLK 6 PCICLK PCICLK 2 PCICLK2 2 PCICLK PCICLK Byte : Control Register ( = enable, = disable) B it Pin# PWD Description 7 8 V66_ V66_ 7 V66_ - X FS# IOAPIC 2 - X FS# CPUCLK 2 CPUCLK Byte : Control Register ( = enable, = disable) Byte 6: Peripheral, Active/Inactive Register (= enable, = disable) B it Pin# PWD Description 7 - (Reserved) 6 - (Reserved) - (Reserved) - (Reserved) 26 SDRAM 2 27 SDRAM SDRAM9 SDRAM8 B it Pin# PWD Description 7 - Reserved (Note) 6 - Reserved (Note) - Reserved (Note) - Reserved (Note) - Reserved (Note) 2 - Reserved (Note) - Reserved (Note) - Reserved (Note) Note: Don t write into this register, writing into this register can cause malfunction Notes: Inactive means outputs are held LOW and are disabled from switching These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation 2 PWD = Power on Default

6 ICS92-2 Absolute Maximum Ratings Core Supply Voltage 6 V I/O Supply Voltage 6V Logic Inputs GND V to V DD + V Ambient Operating Temperature C to +7 C Storage Temperature 6 C to + C Case Temperature C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied Exposure to absolute maximum rating conditions for extended periods may affect product reliability Group Timing Relationship Table CPU to Group CPU to SDRAM to SDRAM V66 V66 CPU 66MHz SDRAM MHz Offset Tolerance CPU MHz SDRAM MHz Offset Tolerance CPU MHz SDRAM MHz Offset Tolerance CPU MHz SDRAM MHz Offset Tolerance 2.ns.ns.ns.7ns 7.ns.ns.ns.ns.ns.ns.ns.7ns V66 to PCI.-.ns.-.ns.-.ns. -.ns PCI to PCI USB & DOT.ns.ns.ns.ns.ns.ns.ns.ns Asynch N/ A Asynch N/ A Asynch Electrical Characteristics - Input/Supply/Common Output Parameters T A = - 7C; Supply Voltage V DD =. V +%, VDDL=2. V+ %(unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Voltage V IH 2 V DD +. V Input Low Voltage V IL V SS -..8 V Input High Current I IH V IN = V DD - µa Input Low Current I IL V IN = V; Inputs with no pull-up resistors - µa Input Low Current I IL2 V IN = V; Inputs with pull-up resistors -2 µa Operating I DD.OP C L = pf; 66M ma Supply Current Power Down I DD.PD C L = pf; With input address to Vdd or GND 6 µa Supply Current Input frequency F i V DD =. V;.8 MHz Pin Inductance L pin 7 nh Input Capacitance C IN Logic Inputs pf C out Out put pin capacitance 6 pf C INX X & X2 pins 27 pf Transition Time T trans To st crossing of target Freq. ms Settling Time T s From st crossing to % target Freq. ms Clk Stabilization T STAB From V DD =. V to % target Freq. ms Delay t PZH,t PZH output enable delay (all outputs) ns t PLZ,t PZH output disable delay (all outputs) ns Guarenteed by design, not % tested in production. N/ A Asynch N/ A 6

7 ICS92-2 Electrical Characteristics - CPU T A = - 7C, V DDL = 2. V +/-%; C L = - 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R DSP2B V O = V DD *(.). Ω R DSN2B V O = V DD *(.). Ω Output High Voltage V OH2B I OH = - ma 2 V Output Low Voltage V OL2B I OL = ma. V Output High Current I OH2B V =.V, V OH@ MAX = 2.7V ma Output Low Current I OL2B V =.2V, V OL@ MAX =.V 27 ma Rise Time t r2b V OL =. V, V OH = 2. V..6 ns Fall Time t f2b V OH =. V, V OL = 2. V..6 ns Duty Cycle d t2b V T =.2 V ns Skew t sk2b V T =.2 V 7 ps Jitter t jcyc-cyc V T =.2 V 2 ps Guarenteed by design, not % tested in production. Electrical Characteristics - V66 T A = - 7C; V DD =. V +/-%; C L = - pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R DSP V O = V DD *(.) 2 Ω R DSN V O = V DD *(.) 2 Ω Output High Voltage V OH I OH = - ma 2. V Output Low Voltage V OL I OL = ma. V Output High Current I OH VOH@ MIN =. V, VOH@ MAX =. V - - ma Output Low Current I OL VOL@ MIN =.9 V, VOL@ MAX=. 8 ma Rise Time t r V OL =. V, V OH = 2. V..6 ns Fall Time t f V OH = 2. V, V OL =. V..6 ns Duty Cycle d t V T =. V % Skew t sk V T =. V 7 ps Jitter t jcyc-cyc V T =. V ps Guarenteed by design, not % tested in production. 7

8 ICS92-2 Electrical Characteristics - IOAPIC T A = - 7C;V DDL = 2. V +/-%; C L = - 2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R DSPB V O = V DD *(.) 9 Ω R DSNB V O = V DD *(.) 9 Ω Output High Voltage V OH\B I OH = -. ma 2 V Output Low Voltage V OLB I OL = 9. ma. V Output High Current I OHB V OH@ min =. V, V OH@ MAX = 2. V -6-2 ma Output Low Current I OLB V OL@ MIN =. V, V OL@ MAX=.2 6 ma Rise Time t rb V OL =. V, V OH = 2. V..6 ns Fall Time t fb V OH = 2. V, V OL =. V..6 ns Duty Cycle d tb V T =.2 V % Jitter t jcyc-cyc V T =.2 V ps Guarenteed by design, not % tested in production. Electrical Characteristics - SDRAM T A = - 7C; V DD = V DDL =. V +/-%; C L = 2 - pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R DSP V O = V DD *(.) 2 Ω R DSN V O = V DD *(.) 2 Ω Output High Voltage V OH I OH = - ma 2. V Output Low Voltage V OL I OL = ma. V Output High Current I OH V = 2. V, V OH@ MAX =. V - -6 ma Output Low Current I OL V OL@ MIN =. V, V OL@ MAX =. V ma Rise Time T r V OL =. V, V OH = 2. V..6 ns Fall Time T f V OH = 2. V, V OL =. V..6 ns Duty Cycle D t V T =. V % Skew T sk V T =. V 2 ps Jitter t j cyc-cyc V T =. V 2 ps Guarenteed by design, not % tested in production. 8

9 ICS92-2 Electrical Characteristics - PCI T A = - 7C; V DD =. V +/-%; C L = - pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R DSP V O = V DD *(.) 2 Ω R DSN V O = V DD *(.) 2 Ω Output High Voltage V OH I OH = - ma 2. V Output Low Voltage V OL I OL = ma. V Output High Current I OH VOH@ MIN =. V, VOH@ MAX =. V - - ma Output Low Current I OL VOL@ MIN =.9 V, VOL@ MAX=. 8 ma Rise Time t r V OL =. V, V OH = 2. V. 2 ns Fall Time t f V OH = 2. V, V OL =. V. 2 ns Duty Cycle d t V T =. V % Skew t sk V T =. V ps Jitter t jcyc-cyc V T =. V ps Guarenteed by design, not % tested in production. Electrical Characteristics - 8M, REF T A = - 7C; V DD = V DDL =. V +/-%; C L = -2 pf (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS R DSP V O = V DD *(.) 2 6 Ω R DSN V O = V DD *(.) 2 6 Ω Output High Voltage V OH I OH = ma 2. V Output Low Voltage V OL I OL = - ma. V Output High Current I OH V = V, V OH@MAX =. V ma Output Low Current I OL V OL@MIN =.9 V, V OL@MIN =. V ma Rise Time t r V OL =. V, V OH = 2. V.8 ns Fall Time t f V OH = 2. V, V OL =. V.7 ns Duty Cycle d t V T =. V % Jitter t jcyc-cyc V T =. V; Fixed Clocks ps t jcyc-cyc Guarenteed by design, not % tested in production. V T =. V; Ref Clocks ps 9

10 ICS92-2 General I 2 C serial interface information The information in this section assumes familiarity with I 2 C programming For more information, contact ICS for an I 2 C programming application note How to Write: Controller (host) sends a start bit Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte ) through byte ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit How to Read: Controller (host) will send start bit Controller (host) sends the read address D (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte ) through byte Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit Notes: 2 6 Controller (Host) Start Address D2 (H) Dummy Command Code Dummy Byte Count Byte Byte Byte 2 Byte Byte Byte Stop How to Write: ICS (Slave/Receiver) Controller (Host) Start Address D (H) ICS (Slave/Receiver) Byte Count The ICS clock generator is a slave/receiver, I 2 C component It can read back the data stored in the latches for verification Read-Back will support Intel PIIX "Block-Read" protocol The data transfer rate supported by this clock generator is K bits/sec or less (standard mode) The input is operating at V logic levels The data byte format is 8 bit bytes To simplify the clock generator I 2 C interface, the protocol is set to use only "Block-Writes" from the controller The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes The data is loaded until a Stop sequence is issued At power-on, all registers are set to a default condition, as shown Stop How to Read: Byte Byte Byte 2 Byte Byte Byte

11 ICS92-2 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS92-2 serve as dual signal functions to the device During initial power-up, they act as input pins The logic level (voltage) that is present on these pins at this time is read and stored into a - bit internal data latch At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function In this mode the pins produce the specified buffered clocks to external loads Figure shows a means of implementing this function when a switch or 2 pin header is used With no jumper is installed the pin will be pulled high With the jumper in place the pin will be pulled low If programmability is not necessary, than only a single resistor is necessary The programming resistors should be located close to the series termination resistor to minimize the current loop area It is more important to locate the series termination resistor close to the driver than the programming resistor To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic ) power supply or the GND (logic ) voltage potential A Kilohm (K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period Programming Header Via to Gnd 2K Via to VDD Device Pad Series Term. Res. 8.2K Clock trace to load Fig.

12 ICS92-2 Power Down Waveform Note After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion 2 Power-up latency <ms Waveform shown for MHz 2

13 ICS92-2 ns ns 2ns ns ns Cycle Repeats CPU 66MHz CPU MHz CPU MHz SDRAM MHz SDRAM MHz.V 66MHz PCI MHz APIC MHz REF.8MHz USB 8MHz Group Offset Waveforms

14 ICS92-2 SYMBOL In Millimeters COMMON DIMENSIONS In Inches COMMON DIMENSIONS MIN MAX MIN MAX A A b c D SEE VARIATIONS SEE VARIATIONS E E e.6 BASIC.2 BASIC h L N SEE VARIATIONS SEE VARIATIONS α 8 8 VARIATIONS D mm. D (inch) N MIN MAX MIN MAX JEDEC MO-8 DOC# - 6// REV B Ordering Information ICS92yF-2-T Example: ICS XXXX y F - PPP - T Designation for tape and reel packaging Pattern Number (2 or digit number for parts with ROM code patterns) Package Type F=SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of or digit numbers) Prefix ICS, AV = Standard Device PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.