Mohit Arora. The Art of Hardware Architecture. Design Methods and Techniques. for Digital Circuits. Springer

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1 Mohit Arora The Art of Hardware Architecture Design Methods and Techniques for Digital Circuits Springer

2 Contents 1 The World of Metastability Introduction Theory of Metastability Metastability Window Calculating MTBF Avoiding Metastability Using a Multi-stage Synchronizer Multi-stage Synchronizer Using Clock Boost Circuitry Metastability Test Circuitry Types of Synchronizers Metastability/General Recommendations 10 2 Clocks and Resets Introduction Synchronous Designs Avoid Using Ripple Counters Gated Clocks Double-Edged or Mixed Edge Clocking Flip Flops Driving Asynchronous Reset of Another Flop Recommended Design Techniques Avoid Combinational Loops in Design Avoid Delay Chains in Digital Logic Avoid Using Asynchronous Based Pulse Generator Avoid Using Latches Avoid Using Double-Edged Clocking Clocking Schemes Internally Generated Clocks Divided Clocks Ripple Counters Multiplexed Clocks Synchronous Clock Enables and Gated Clocks 26 xi

3 xjj Contents 2.5 Clock Gating Methodology Latch Free Clock Gating Circuit Latch Based Clock Gating Circuit Gating Signals Data Path Re-ordering to Reduce Switching Propagation Reset Design Strategy Design with Synchronous Reset Design with Asynchronous Reset Flip Flops with Asynchronous Reset and Asynchronous Set Asynchronous Reset Removal Problem Reset Synchronizer Reset Glitch Filtering Controlling Clock Skew Short Path Problem Clock Skew and Short Path Analysis Minimizing Clock Skew 46 References 49 3 Handling Multiple Clocks Introduction Multiple Clock Domains Problems with Multiple Clock Domains Design Setup Time and Hold Time Violation Metastability Design Tips for Efficient Handling of a Design with Multiple Clocks Clock Nomenclature Design Partitioning Clock Domain Crossing Synchronous Clock Domain Crossing Clocks with the Same Frequency and Zero Phase Difference Clocks with the Same Frequency and Constant Phase Difference Clocks with the Different Frequency and Variable Phase Difference Handshake Signaling Method Requirements for Handshake Signaling Disadvantages of Handshake Signaling Data Transfer Using Synchronous FIFO Synchronous FIFO Architecture 67

4 Contents xiii Working of Synchronous FIFO Asynchronous FIFO (or Dual Clock FIFO) Avoid Using B inary Counters for the Pointer Implementation Use Gray Coding Instead of Binary for the Counters Gray Code Implementation of FIFO Pointers FIFO Full and FIFO Empty Generation Dual Clock FIFO Design 82 References 86 4 Clock Dividers Introduction Synchronous Divide by Integer Value Odd Integer Division with 50% Duty Cycle Non-integer Division (with a Non 50% Duty Cycle) Divide by 1.5 with Non 50% Duty Cycle Counter Implementation for Divide by 4.5 (Non 50% Duty Cycle) Alternate Approach for Divide by N LUT Implementation for Divide by Reference 93 5 Low Power Design Introduction Sources of Power Consumption Power Reduction at Different Levels of Design Abstraction System Level Power Reduction System on Chip (SoC) Approach Hardware/Software Partitioning Low Power Software Choice of Processor Architecture Level Power Reduction Advanced Clock Gating Dynamic Voltage and Frequency Scaling (DVFS) Cache Based Architecture Log FFT Architecture Asynchronous (Clockless) Design Power Gating Multi-threshold Voltage Ill Multi-supply Voltage Gate Memory Power Register Transfer Level (RTL) Power Reduction State Machine Encoding and Decomposition Binary Number Representation 114

5 A x v Contents Basic Gated Clock One Hot Encoded Multiplexer Removing Redundant Transactions Resource Sharing Using Ripple Counters for Low Power Bus Inversion High Activity Nets Enabling-Disabling Logic Clouds Transistor Level Power Reduction Technology Level Layout Optimization Substrate Biasing Reduce Oxide Thickness Multi-oxide Devices Minimizing Capacitance by Custom Design 128 References The Art of Pipelining Introduction Factors Affecting the Maximum Frequency of Clock Clock Skew Clock Jitter Pipelining Pipelining Explained - Real Life Example Performance Increase from Pipelining Implementation of DLX Instruction Effect of Pipelining on Throughput Pipelining Principles Pipelining Hazards Structural Hazards Data Hazards Control Hazards Other Hazards Pipelining in ADC - An Example 152 References Handling Endianness Introduction Definition Little-Endian or Big-Endian: Which Is better? Issues Dealing with Endianess Mismatch Accessing 32 Bit Memory Dealing with Endianness Mismatch 161

6 Contents xv Preserve Data Integrity (Data Invariance) Address Invariance Software Byte Swapping Endian Neutral code Endian-Neutral Coding Guidelines 167 References Deboucing Techniques Introduction Behavior of a Switch Switch Types De-bouncing Techniques RC De-bouncer Hardware De-bouncers Software De-bouncing De-bouncing Guidelines De-bouncing on Multiple Inputs Existing Solutions Design Guidelines for EMC Performance Introduction Definition EMI Theory and Relationship with Current and Frequency EMI Regulations, Standards and Certification Factors Affecting IC Immunity Performance Microcontroller as Noise Source Other Factors Affecting EMC Noise Carriers Techniques to Reduce EMC/EMI System Level Techniques Board Level Techniques Microcontroller Level Techniques Software Level Techniques Other Techniques Summary 213 References 214 References 215 Index 219

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