Sequential Logic Circuits

Transcription

1 Exercise 2 Sequential Logic Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of simple sequential logic circuits; - measure the dynamic parameters of asynchronous sequential circuits; - verify the presence of bouncing on mechanical contacts and test anti-bounce circuits; - verify the behavior of a simple Digital/Analog converter. Only the first page of the report form is available for this exercise. Add the required sheets using A4 papers, following the outline used for the previous report. Instruments and circuit setup The required circuits must be arranged on solderless breadboard. If you never used it before, read the document Use of solderless breadboard, on the course web site. Logic circuits use steep edge signals; keep connections as straight and short as possible. The instruments required are - a squarewave generator (frequency range at least 1Hz 10MHz) - a two-channel oscilloscope (bandwidth at least 60 MHz) - switches to set logic states and LEDs or a display to read logic states. The components required are: - Resistors and Capacitors, as detailed for each experiment - Integrated multistage asynchronous counter (CD4040 or CD 4060) - 2-input NAND gates (74HC00) Measurement procedures Circuit operation can be verified using the oscilloscope or a logic analyzer. With scope, use all available channels (up to 4 in some cases). Logical state can be read also connecting LEDs between the output and the voltage supply, with a 3.3 KΩ in series. In the breadboard several LEDs with driving circuit are available. Warning Remember that in CMOS circuits, all inputs must be connected to a well defined logical state! Also remember that the voltage applied to an integrate circuit cannot exceed the supply voltage range (0V to 5 V for the logic circuits used in this experiment). Therefore, set the signal generator before connecting it to the circuit. 1

2 2 - Measurements 2.1 Asynchronous Counter Examine the data sheet of CD4040 counter, in order to identify the function of various inputs. Mount the CD4040 integrated circuit with 5V supply (Vss 0V, Vdd positive voltage supply). Connect the RESET to a proper logical state in order to enable the counting. a) Connect LEDs and a seven-segment display to the first 4 outputs (Q1 Q4). Apply clock from the ob-breadboard variable-frequency squarewave generator. Verify the counting sequence on the LEDs and on the display (reduce the clock frequency as required to see the various logic states). The counter follows a binary sequence, while the display is decimal. Verify what happens for counter states b) Verify (using the oscilloscope) that, on the outputs, every square wave has a frequency which is the half of the previous one. Raise the clock rate as required, and synchronize the timebase of oscilloscope with the lowest frequency signal. c) Verify that the switching delay increases from a Flip-Flop to the next one along the counter chain. In order to execute this step easily, is useful to increase the clock frequency until the clock period becomes comparable with the propagation delay. The delay measurement is more easy between multiple stages (higher delay, better measurement, see next point). Verify that an additional capacitance on a FF output increases the delay. d) Measure the delay of a single counter stage (Flip-Flop), by measuring the delay of a rather long FF chain and then divide it by the number of FlipFlops. Verify that the delay is function of the number of FF between the two measurement points and does not depend on the divider chain position. e) Leave the Clock input unconnected; verify that, in this condition, the input gather noise from the environment (like an antenna): field from the electric network (50 Hz), electric charges from near (not in contact) objects, etc. Verify that touching the monitor screen with one hand and bringing the other hand near the floating input, the counter receives a clock signal by capacitive coupling. Connecting a pullup resistor R PU, the input potential is fixed by the pullup resistor, which has a smaller Z than capacitive coupling, and reduce the noise. (a similar behavior can be seen leaving the reset input pin open). f) Connect a pull-up resistor R PU = 10 kω between the clock input and the positive supply, with a switch towards the ground, or use a wire as contact (diagram on the side). You can now apply the clock signal CK manually, by closing the switch. Verify that whenever you operate the switch (or any contact to ground) several clock pulses are sent (look at the counter state). R PU V AL CK Use the oscilloscope in single-shot mode, and observe bounces on the screen. 2

3 g) Insert the debounce circuit (Flip-Flop SR made with NAND gates 74HC00 see diagram on the side). V AL Verify that with this circuit the counter advances one unit for each operation of the input switch. R PU2 R PU1 S Q* CK A Use the SPDT pushbutton switch available on the breadboard; build the complete debounce circuit, and observe the different behavior (bounce/ bounce removed) moving the Clock connection between the S input and the Q output. B R Q Decoder For the following exercises, reconnect the square wave generator (with proper levels) to the clock input. The integrated counter follows a binary sequence (0 15 in the 4 LSBs), but can be converted to a decade counter (0 9) using the reset command. Using two-input NAND gates create a circuit (decoder) which recognizes the state 1010 (decimal 10, the next state after 9), and use the output to reset the counter. A couple of 2-input NAND gate (left from the 7400 used in the SR FF) allows to build the reset circuit. Verify the operation in static (slow advancement, outputs state verification through LEDs) and dynamic conditions (fast clock, signal verified on the oscilloscope). Block diagram and pins description of CD4040 are in the drawing. Datasheets of other devices are available from the manufacturers sites. 3

4 2.3 D/A Conversion This part of the exercise brings to the realization of a D/A converter based on a set of weighted resistors (ratio 2), directly driven by the counter outputs. The resistor network brings the output Va to a level related with Q3 Q6 counter outputs. Each output Qi provides (through the weighted resistor) a contribution proportional to the weigth (bit position i). Q3 is the LSB, Q6 the MSB. The operation of this D/A converter is described more in detail in lesson F2 of Electronic Systems. Connect the 390K, 180K, 100K, 47K resistors between the counter outputs Q3, Q4, Q5, Q6 and the node A (as shown in the figure). Apply a 100 KHz square wave to the counter clock input. CK CD 4040 Q1 Q2 Q3 Q4 Q5 Q6 Q7. Q12 Nominal actual R1 400 kω 390 kω R2 200 kω 180 kω R3 100 kω 100 kω R4 50 kω 47 kω R1 R2 R3 R4 A Va If resistor of the list are not available, build reasonable approximations using series or parallel of available devices. a) Observe the Va signal on the A node, and the four outputs Q3 Q6; explain the wave shape observed on A node, and the relation with square waves on Q3 6. b) Add a 820 kω resistor between Q2 and node A; verify and explain the effect on Va. c) Remove R5, than add a 27 kω resistor (R7) between Q7 and node A; verify and explain the effect on Va. d) How are the steps on Va modified by a 220 kω resistor (R7') in parallel to R7? Explain the reasons of the changes. e) How are the steps on Va modified by replacing the 47 kω resistor (R4) with two 100 kω resistors in parallel? Explain the reason. f) What should happen adding a 1.5 MΩ resistor (R6) between Q1 output and node A? (the practical exercise is difficult to perform, because the effect on Va voltage is low). 4

5 3 - Common mistakes and possible failures. One of the most frequent reason of failures in this exercise are false contacts in the breadboard. Read carefully the instructions on the document Use of solderless breadboard (learning material Use of solderless breadboard). In case of malfunction, apply the following steps: a) If wires for connection are oxidized, or twisted, or bent, use new ones. b) Do not insert segments of insulated wires in the breadboard holes: spring-shaped internal contacts can touch the insulator instead of the metal. In such case the connection seems to be correct, but the electric connection is not present. c) Verify the components value (don't trust the labels on the drawer). d) Verify signals and power supply, directly on the IC circuit, touching the pins with the probe metal tip (to identify false contacts between the breadboard and the IC pins). e) Verify the contacts between clamps (supply and signals) and breadboard connection wires. Remove insulator from the piece of wire inserted in the clamp.. f) If the D/A converter output characteristic appears non-monotone, verify resistor values and their positions in the counter outputs sequence (on Q6 output should be present a square wave at the lowest frequency). 5

6 4. -Report form (draft) Digital Electronics - Exercise 2:... Date: Team ; composition: role name Student ID signature Measurements Report writing Instruments used Instrument Brand and type characteristics Signal generator: Oscilloscope Digital circuits Breadboard unit Brief description of goals 6

7 History of the document DDC last revision (italian) PL translation DDC translation verification DDC small corrections DDC adaptation for Tongij lab 7