Sequential Logic Circuits

Transcription

1 LAB EXERCISE - 5 Page 1 of 6 Exercise 5 Sequential Logic Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of simple sequential logic circuits; - measure the dynamic parameters of asynchronous sequential circuits; - verify the presence of bouncing on mechanical contacts; - verify the behavior of a simple Digital/Analog converter. The pre-compiled form for the report is not available for this exercise. Use A4 papers, following the outline used for the previous report. Circuits and instruments The required circuits must be arranged on solderless breadboard. If you never used it before, read the document Use of solderless breadboard, on the course web site. Measurement procedures Circuit operation can be verified using the oscilloscope. It is useful to use all available channels. Some 4 channel scopes have fixed gain on on channels 3 and 4. Use a voltage divider to obtain signals with amplitude similar the ones on main channels 1 and 2. Logical state can be read also connecting LEDs between the output and the voltage supply, with a 3.3 KΩ in series. In the LADISPE a board with 8 LED+resistor pairs is available.. Warning Remember that in CMOS circuits, all inputs must have to be connected to a well defined logical state! Also remember that the voltage applied to an integrate circuit cannot exceed the supply voltage range (0V to 5 V for the logic circuits used in this experiment). Set the signal generator before connecting it to the circuit.

2 LAB EXERCISE - 5 Page 2 of Measurements 2.1 Asynchronous Counter Examine the data sheet of CD4040 counter, in order to identify the function of various inputs. Mount the CD4040 integrated circuit with 5V supply (Vss 0V, Vdd positive voltage supply). Place the components in such a way as to make possible the insertion of other logical integrate circuit (use bus strips for supply voltage ang ground; see the indications in the document Use of solderless breadboard in the Learning Material table). Connect the RESET to a proper logical state in order to enable the counting. a) Connect a square wave to the inputs, with levels 0.5/3.5 V (to be checked before connecting the signal generator to the circuit). Verify (using the oscilloscope) that, on the outputs, every square wave has a frequency which is the half of the previous one. Synchronize the timebase of oscilloscope with the lowest frequency signal. b) Verify that the switching delay increases from a Flip-Flop to the next one along the counter chain. In order to execute this step easily, is useful to increase clock frequency until the clock period becomes comparable with the propagation delay. c) Measure the delay of a single counter stage (Flip-Flop), by measuring the delay of a rather long FF chain and then divide it by the number of FlipFlops. Verify that the delay is function of the number of FF between the two measurement points and not function of the divider chain position. d) Insert some LEDs on the first outputs, as indicated in the section Measurement procedures in the previous section. Reduce the clock frequency until you can verify the counting sequence on the LEDs (using LEDs is possible to look over several outputs at the same time; this is not possible with oscilloscope). e) Disconnect the clock provided by the signal generator; and connect a pull-up resistor R PU = 10 kω between the clock input and the positive supply, with a switch towards the round, or use a wire as contact (diagram on the side). You can now apply the clock signal CK manually, by closing the switch. Verify that whenever you operate the switch (or any contact to ground) several clock pulses are sent (look at the counter state). R PU V AL CK f) Remove the pull-up resistor and leave the input unconnected; verify that, in this condition, the input gather noise from the environment (like an antenna): field from the electric network (50 Hz), electric charges from near (not in contact) objects, etc. Verify that touching the monitor screen with one hand and bringing the other hand near the floating input, the counter receives a clock signal by capacitive coupling. Reconnecting R PU, the input potential is fixed by the pull-up resistor, which has a smaller Z than capacitive coupling, and reduce the noise. (the same check can be done on the reset input).

3 LAB EXERCISE - 5 Page 3 of 6 g) Insert the debounce circuit (Flip-Flop SR made-up of NAND gates 74HC00 see diagram on the side). Verify that with this circuit the counter advances one unit for each operation of the input switch. V AL R PU2 R PU1 S A Q* CK B R Q Decoder For the following exercises, reconnect the square wave generator (with proper levels) to the clock input. Using two-input NAND gates create a circuit (decoder) which recognizes the state 111 on the first three counter stages (Flip-Flop outputs). Verify the operation in static (slow advancement, outputs state verification through LEDs) and dynamic conditions (fast clock, signal verified on the oscilloscope). Block diagram and pins description of CD4040 are in the drawing. Datasheets of other devices are available on LADISPE site, on the course Website (ULISSE) or from the manufacturers sites.

4 LAB EXERCISE - 5 Page 4 of D/A Conversion This part of the exercise brings to the realization of a D/A converter based on a set of weighted resistors (ratio 2), directly driven by the counter outputs. The operation of this D/A converter is described in lesson F2. Connect the 390K, 180K, 100K, 47K resistors between the counter outputs Q3, Q4, Q5, Q6 and the node A (as shown in the figure). Apply a 100 KHz square wave to the counter clock input. CK CD 4040 Q1 Q2 Q3 Q4 Q5 Q6 Q7. Q12 Nominal actual R1 400 kω 390 kω R2 200 kω 180 kω R3 100 kω 100 kω R4 50 kω 47 kω R1 R2 R3 R4 A Va a) Observe the Va signal on the A node, and the four outputs Q3 Q6; explain the wave shape observed on A node, and the relation with square waves on Q3 6. b) Add a 820 kω resistor between Q2 and node A; verify and explain the effect on Va. c) Remove R5, than add a 27 kω resistor (R7) between Q7 and node A; verify and explain the effect on Va. d) How are the steps on Va modified by a 220 kω resistor (R7') in parallel to R7? Explain the reasons of the changes. e) How are the steps on Va modified by replacing the 47 kω resistor (R4) with two 100 kω resistors in parallel? Explain the reason. f) What should happen adding a 1.5 MΩ resistor (R6) between Q1 output and node A? (the practical exercise is difficult to perform, becuse the effect on Va voltage is low).

5 LAB EXERCISE - 5 Page 5 of Common mistakes and possible failures. One of the most frequent reason of failures in this exercise are false contacts in the breadboard. Read carefully the instructions on the document Use of solderless breadboard (learning material Use of solderless breadboard). In case of malfunction, apply the following steps: a) If wires for connection are oxidized, or twisted, or bent, use new ones. b) Do not insert segments of insulated wires in the breadboard holes: spring-shaped internal contacts can touch the insulator instead of the metal. In such case the connection seems to be correct, but the electric connection is not present. c) Verify the components value (don't trust the labels on the drawer). d) Verify signals and power supply, directly on the IC circuit, touching the pins with the probe metal tip (to identify false contacts between the breadboard and the IC pins). e) Verify the contacts between clamps (supply and signals) and breadboard connection wires. Remove insulator from the piece of wire inserted in the clamp.. f) If the D/A converter output characteristic appears non-monotone, verify resistor values and their positions in the counter outputs sequence (on Q6 output should be present a square wave at the lowest frequency).

6 LAB EXERCISE - 5 Page 6 of 6 History of the document DDC last revision (italian) PL translation DDC translation verification DDC small corrections