9 Asynchronous Counter:3 bit up/down counter

Transcription

1 9 Asynchronous Counter:3 bit up/down counter Aim: To design and setup a 3 bit asynchronous Up/Down Counter Components required Digital IC trainer kit,ic 7473 Dual JK Flip Flop with active RESET,IC 7400 Quad 2 input NAND gates,ic 7486 Quad 2 input EXOR gates. Comparing the asynchronous up and down counter we see that for an asynchronous up counter the Q output of each flip fop is connected to clock input of next flipflop. While in case of asynchronous down counter the (Q)output of each flipflop is connected to clock input of next flipflop. We can use a mode control(select input M) to select between Q and Q. For M=0 we need the counter to count up and for M=1 and we need to count down. Clock input of each stage n+1 is MQ n + MQ n = M Q n Logic Circuit Design Lab Page 1

2 Fig. 9.1: 3bit Asynchronous UP-DOWN Counter Logic Circuit Design Lab Page 2

3 Procedure: 1. Assemble the circuit neatly on the breadboard. 2. Connect the switch SW1 to ground (logic 0). Since SW1 is connected to Rof all flip-flops all the flip-flop outputs gets reset(q=0). 3. Now to resume normal operation we need to make Rhigh. So flip the switch to high (logic 1). 4. To count up select M=0 (flip SW2 to ground) Now apply the clock pulse and verify the output patterns. 5. To count down select M=1(flip SW2 to high) Now apply the clock pulse and verify the output patterns. Additional Questions: 1. Compare the advantages and disadvantages of asynchronous counters. Additional Design Question: 2. Design a MOD-10 asynchronous counter using D flipflops. Result: Designed and setup an asynchronous down, asynchronous up, asynchronous decade and asynchronous up/down counter. Logic Circuit Design Lab Page 3

4 A LTSpice Simulations PRESETTING and CLEARING of Flip flops: The flip flops outputs can be in any one of the stable states during power up.for certain circuits (expecially for Ring Counter) it is necessary that the flip flops output should be in one of the predefined states.for example for counters starting count at 0 we must have all flip flop outputs be at zero during starting.this requirement can be met using PRE/CLR inputs.in case of a practical circuit this can be attained by using switches.for most flip flps with active low PRESET and CLEAR this requires the precise changing of switches from HIGH to LOW to HIGH. For LTspice we donot have run time changes in simulations so we cannot change the states of swicthes easily.so an alternate circuit as shown belo is used for CLEARING/PESETTING of flip flop outputs.the working of the circuit can be explained as follows.initally for CLEARING/PRESETTING the flip flop output we need a active low output that is 0.The circuit acts as a short circuit initially and output is 0.This PRESETS/CLEAR the flip flop.now we need to resume normal operation of flip flop.for this the PRESET/CLEAR signal should change to HIGH.The capacitor slowly charges towards to VCC or HIGH and after 5 time constants the output is HIGH and normal operation of flip flop can be resumed.the time constant is taken as 1ms for which we can use C=1uF and R=1k. Fig. A.1: Triggering Circuit for Flip Flops. Fig. A.2: Triggering Circuit for Flip Flops Output: Logic Circuit Design Lab Page 4

5 A.1 Asynchronous Counter: Realization of 4-bit up and down counter: Fig. A.3: 4bit asynchronous up counter. Fig. A.4: Timing diagram for 4bit asynchronous up counter: LTspice Simulation File: Logic Circuit Design Lab Page 5

6 4bit up counter illustrating the delay problem.as the frequency approaches very high around MHz range. Fig. A.5: 4bit asynchronous up counter. Fig. A.6: Timing diagram for 4bit asynchronous up counter: LTspice Simulation File: Logic Circuit Design Lab Page 6

7 Fig. A.7: 4bit asynchronous down counter. Fig. A.8: Timing diagram for 4bit asynchronous down counter: LTspice Simulation File: Logic Circuit Design Lab Page 7

8 B 4bit Asynchronous UP/DOWN Counter: (a) 4bit asynchronous Up Counter (b) 4bit asynchronous Down Counter Fig. B.1: 4bit asynchronous Up/Down Counter Logic Circuit Design Lab Page 8