Name EGR 2131 Lab #2 Logic Gates and Boolean Algebra Objectives Equipment and Components Part 1: Reading Pin Diagrams 7400 (TOP VIEW)

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1 Name EGR 23 Lab #2 Logic Gates and Boolean Algebra Objectives ) Become familiar with common logic-gate chips and their pin numbers. 2) Using breadboarded chips, investigate the behavior of NOT (Inverter), OR, AND, NOR, NAND logic gates. 3) Understand how various gates can be used for Enable/Disable purposes. 4) Use logic gates to demonstrate some rules of Boolean algebra. Equipment and Components Safety glasses ETS-7 Digital-Analog Training System Tektronix TDS24 Digital Storage Oscilloscope ICs: 74, 742, 744, 748, 7432 Part : Reading Pin Diagrams To make connections in a circuit using ICs, you must be able to identify pin numbers, and identify each IC s power and ground pins. An example using the 74 chip is shown below. This IC has four 2-input NAND gates inside it. For one of these NAND gates, pins and 2 are the inputs and pin 3 is the output. 74 (TOP VIEW) No matter who the manufacturer is, pin numbers are standard. The 74 shown above is in a 4-pin Dual-in-Line package (DIP). The pin numbers are read -to-7 on one side (with pin on the left), as shown above. Pin 8 is right across from pin 7 and you read pins 8-to-4 on the other side, from right to left. Notice that the notch (or sometimes a dot) on one end of the DIP helps you orient it, as shown above. Sometimes pin may be identified by a printed on the package. EGR 23 Lab #2 - Page Revised 2/2/28

2 . Using Texas Instruments website ( draw gate symbols inside the IC outlines given below. Also label each pin with its pin number, as on the previous page Part 2: Testing Gates on the Breadboard [A] Inverter.. Place an inverter chip (744) on the breadboard and provide it with power and ground. 2. Connect the first inverter s input (labeled x below) to one of the trainer s data switches. Connect the same inverter s output (labeled f) to one of the trainer s LEDs. 3. Test the inverter by observing the LED as you use the data switch to apply a HIGH () or a LOW () to the inverter s input. Record your observations in Truth Table. Truth Table 4. Ask me to check your work. Safety glasses? Circuit works? DIP inserted correctly? Using power/ground busses? Wire colors? 5. You re finished with this circuit and can take it apart. Input x EGR 23 Lab #2 - Page 2 Revised 2/2/28 Output f

3 [B] AND Gate.. Place a 2-input AND chip (748) on the breadboard and provide it with power and ground. Connect pins and 2 to two of the trainer s data switches, and connect pin 3 to an LED. Then complete Truth Table 2. Truth Table 2 x y f Does your truth table seem correct for a 2-input AND gate? If so, take the circuit apart. [C] NAND Gate.. Label the gate shown below with its chip number and pin numbers. 2. Breadboard the gate, test it, and draw a complete truth table for it (Truth Table 3). 3. Ask me to check your work. Safety glasses? Circuit works? DIPs inserted correctly? Using power/ground busses? Wire colors? 4. Take the circuit apart. EGR 23 Lab #2 - Page 3 Revised 2/2/28

4 [D] OR Gate.. In the diagram shown below, label each gate with its chip number and pin numbers. 2. Breadboard the circuit, then test it using switches and an LED. Draw a complete truth table for it (Truth Table 4). 3. Ask me to check your work. Safety glasses? Circuit works? DIPs inserted correctly? Using power/ground busses? Wire colors? 4. You re finished with this circuit and can take it apart. [E] A More Complex Circuit. In the diagram below, label each gate with its chip number and pin numbers. 2. Breadboard the circuit, test it, and complete Truth Table 5. Truth Table 5 x y f 3. Ask me to check your work. Safety glasses? Circuit works? DIPs inserted correctly? Using power/ground busses? Wire colors? 5. You re finished with this circuit and can take it apart. EGR 23 Lab #2 - Page 4 Revised 2/2/28

5 Part 3: Using Gates for Enable/Disable. With the trainer s power turned off, connect an AND gate as shown below. Set the trainer s function generator to produce a 2 khz square wave at the TTL MODE terminal. To set your frequency accurately to 2 khz, use the Fluke 45 to measure the frequency. Don t rely on the labels next to the trainer s Frequency knob. Display the TTL MODE signal on the oscilloscope s Channel, and display output f on Channel 2. Don t display Channels 3 and 4. Set each channel s VOLTS/DIV setting to 5 V, and adjust the SEC/DIV control so that about four or five cycles of the waveforms are displayed. Below, use a straight-edge to draw the output f, first with the data switch set High, and then with the data switch set Low. If either output waveform is a flat line, label it as LOW or HIGH. TTL Mode Output f when Switch is High Output f when Switch is Low 2. Ask me to check your work. 3. Next, modify your circuit in the following way: Replace the AND gate with an OR gate. Set the trainer s function generator to produce a 7 Hz square wave at the TTL MODE terminal. To set your frequency accurately, use the Fluke 45 to measure the frequency. Don t rely on the labels next to the trainer s Frequency knob. On the next page, use a straight-edge to draw the output f, first with the data switch set High, and then with the data switch set Low. If either output waveform is a flat line, label it as LOW or HIGH. EGR 23 Lab #2 - Page 5 Revised 2/2/28

6 TTL Mode Output f when Switch is High Output f when Switch is Low 5. Ask me to check your work.. Then take the circuit apart. Part 4: Demonstrating Some Rules of Boolean Algebra Let s see how we can use breadboarded logic circuits to demonstrate three rules of Boolean algebra. The other rules of Boolean algebra could be demonstrated in a similar way. [A] Input x (from TTL Mode) Output f. Label the drawing above with chip number and pin numbers. 2. On the breadboard, connect two inverters as shown in the drawing. 3. For the circuit s input, use a 75 Hz square wave from the trainer s TTL MODE terminal. To set your frequency accurately, use the Fluke 45 to measure the frequency. Don t rely on the labels next to the trainer s Frequency knob. 4. Use your oscilloscope s Channel to display the input waveform x, and use Channel 2 to display the output waveform f. Turn off Channels 3 and Set each channel s VOLTS/DIV setting to 5 V, and adjust the SEC/DIV control so that about four or five cycles of the waveforms are displayed. 6. Arrange the waveforms with x in the screen s top half and f in the bottom half. 7. Use the MEASURE button to display the frequencies of both channels. 8. Ask me to check your work. 9. Question: Which rule of Boolean algebra does this circuit demonstrate? Give the rule s number and the actual statement of the rule. (Example: Rule 6b, x + = x. ) EGR 23 Lab #2 - Page 6 Revised 2/2/28

7 [B] Input x (from TTL Mode) Output f. Label the drawing above with chip numbers and pin numbers. 2. On the breadboard, connect two gates as shown in the drawing. 3. Change the TTL mode frequency to 6 Hz. 4. Display input x on your oscilloscope s Channel, and output f on Channel 2. Don t display Channels 3 or Adjust the SEC/DIV control so that about four or five cycles of the input waveform are displayed. 6. Use the MEASURE button to display the frequencies of Channels and Ask me to check your work. 8. Question: Which rule of Boolean algebra does this circuit demonstrate? [C]. In the space above, draw a logic circuit that demonstrates Rule 7a, x x = x. Label your drawing with chip number and pin numbers.. On the breadboard, build your circuit, using the trainer s TTL terminal for your input. 2. Display your circuit s input and output waveforms on the oscilloscope. 3. Ask me to check your work. EGR 23 Lab #2 - Page 7 Revised 2/2/28

8 Part 5: Review Questions.. How many NAND gates are there in one 74 chip? 2. How many NOT gates (inverters) are there in one 744 chip? 3. Of the following four chips--74, 742, 748, and which one is different from the other three in how the gates are laid out on the chip? Describe this difference. 4. Suppose you didn t have any 742 chips, but you needed to build a circuit equivalent to one of the gates on a 742. Which two chip numbers would you use? Draw a gate diagram showing how you would connect the gates from these two other chips. 5. Based on your observations in the first half of Part 3, explain the enable/disable function of an AND gate. In other words, explain how an AND gate can be used to pass or stop data applied to one of its inputs. Use complete sentences. 6. OR gates can also be used to perform an enable/disable function. Based on your observations in the second half of Part 3, how is an OR gate s behavior similar to an AND gate s behavior when both are used to perform the enable/disable function? How are they different? Use complete sentences. EGR 23 Lab #2 - Page 8 Revised 2/2/28