Exercise 1: AND/NAND Logic Functions
|
|
|
- Giles Sutton
- 6 years ago
- Views:
Transcription
1 Exercise 1: AND/NAND Logic Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the operation of an AND and a NAND logic gate. You will verify your results by generating truth tables for each function. EXERCISE DISCUSSION The schematic symbol of a two-input AND gate and the Boolean equation for the AND gate are shown here. Input signals are labeled A and B, and the output is labeled C. The Boolean equation for the AND gate states that C is high when A and B are high. The AND operation is indicated by the dot between A and B. NOTE: A B and AB without the are identical. The schematic symbol of a two-input NAND gate and the Boolean equation for the NAND gate are shown here. 48 FACET by Lab-Volt
2 Fundamental Logic Elements The Boolean equation for the NAND gate states that C is low when A and B are high. The bar over A B represents the complement. The NAND gate function has a bubble drawn at the output side of the gate. The bubble indicates a complement. Pins 14 and 7 supply power to the IC. The IC provides four separate two-input NAND gates labeled A through D. FACET by Lab-Volt 49
3 Pin 11 is the output for which gate? a. A b. B c. C d. D For the 74LS00 IC, inputs may be tied to other inputs, or outputs may be connected to inputs; however, outputs cannot be connected to one another. Unused inputs generally are pulled high (connected to 5 Vdc) through a pull-up resistor. Two NAND gates can be cascaded (connected in series) to generate an AND operation, as shown. Output C provides a NAND response to circuit inputs A and B. Output C is complemented by the action of GATE 2. In turn, this gate generates an AND operation for circuit inputs A and B at output D. This is the truth table for the circuit. 50 FACET by Lab-Volt
4 Fundamental Logic Elements Outputs C and D are complements. Output column C provides the NAND function truth table, while output column D provides the AND function truth table. A and B are the two circuit inputs. Four unique input conditions test all possible input combinations. A low logic state at any input disables an AND gate. A high logic state at one input of a two-input AND gate enables the gate. The disable and enable combinations and the truth tables for an AND gate are shown here. If one input is held low, the output is always low and the gate is disabled. FACET by Lab-Volt 51
5 If one input is held high, the output is the same level as the other input and the gate is enabled. If you wanted to disable an AND gate, you would pull one input a. high. b. low. A low level at any input disables a NAND gate. A high level at one input of a NAND gate enables the gate. The disable and enable combinations and the truth tables for a NAND gate are shown here. A disabled NAND gate locks out its other input and generates a high level (1) output, as shown in the truth table. 52 FACET by Lab-Volt
6 Fundamental Logic Elements An enabled NAND gate complements the other input, as shown in the truth table. An eight-input NAND gate (74LS30) is shown. The operating principles of a two-input NAND gate apply to gates having more than two inputs. The output of this gate is low only when all inputs are high. Any one input at a low level locks out the other inputs (the output is always high). PROCEDURE Locate the AND/NAND circuit block, and connect the circuit shown. Activate BLOCK SELECT. Place both toggle switches in the LOW position. NOTE: A high logic level turns on an LED. You can verify the state of a signal, as indicated by a circuit LED, by connecting your multimeter to the appropriate test point. FACET by Lab-Volt 53
7 What are the logic levels at AND gate inputs A and B? a. both low b. both high Based on the input levels, what is the AND gate output level? What are the logic levels at the NAND gate inputs? a. both low b. both high What is the logic level at the output of the NAND gate? 54 FACET by Lab-Volt
8 Fundamental Logic Elements The table shows the AND and NAND outputs when inputs A and B are low. Place toggle switch A in the HIGH position. What is the AND gate output? What is the NAND gate output? Place toggle switch A in the LOW position and switch B in the HIGH position. What is the AND gate output? What is the output of the NAND gate? FACET by Lab-Volt 55
9 Set both switches A and B high. What is the AND output? What is the NAND gate output? Based on the truth table, when is the AND gate output high? a. when any input is high b. when both inputs are high Based on the truth table, are the outputs of the AND and NAND gates complementary? a. yes b. no 56 FACET by Lab-Volt
10 Fundamental Logic Elements Connect the circuit shown here. Connect channel 1 of your oscilloscope to circuit input B. Use channel 2 to monitor other circuit points as required. NOTE: LEDs will appear to be constantly on due to the pulse train input signal. This action does not alter the expected circuit operation. You may disable the circuit block LEDs by removing BLOCK SELECT. Place switch A in the LOW position. Circuit input signal B is a square wave pulse train as seen on oscilloscope channel 1. Monitor the AND gate and NAND gate outputs on channel 2 of the scope. Are the gates enabled or disabled? a. enabled b. disabled Is the AND gate output high or low? a. high b. low FACET by Lab-Volt 57
11 Is the NAND gate output high or low? a. high b. low Place switch A in the HIGH position. Monitor the output of each gate. Are the gates enabled or disabled by the high input at A? a. enabled b. disabled Refer to the waves shown here, and compare the circuit outputs with the circuit input. With respect to input signal B, the AND output is a. in phase. b. out of phase. With respect to input signal B, the NAND gate output is a. in phase. b. out of phase. 58 FACET by Lab-Volt
12 Fundamental Logic Elements CONCLUSION The output of an AND gate is high only when all inputs are high. The output of a NAND gate is low only when all inputs are high. A low input disables an AND or a NAND gate. A high input (two-input gate) will enable an AND or a NAND gate. The output of an enabled AND gate is in phase with its input. The output of an enabled NAND gate is the complement of its input. REVIEW QUESTIONS 1. Locate the AND/NAND circuit block and connect the circuit shown. Disable the circuit gates by placing toggle switch A in the LOW position. Place CM switch 6 in the ON position. The CM a. enables the NAND gate but not the AND gate. b. disables the clock signal at input B. c. enables the AND and NAND gates. d. causes the AND and NAND gate outputs to be in phase. 2. Place CM switch 7 in the ON position. The CM a. places a logic 1 signal at input B to the gates. b. prevents the gates from responding to changes at input A. c. enables the AND gate but disables the NAND gate. d. enables the NAND gate but disables the AND gate. 3. The output of an AND gate is high a. all of the time. b. when any input is low. c. when any input is high. d. when all inputs are high. FACET by Lab-Volt 59
13 4. The output of a NAND gate is low a. all of the time. b. when any input is low. c. when any input is high. d. when all inputs are high. 5. In the circuit shown, output levels A through D are, respectively, a. low, high, low, and low. b. low, high, low, and high. c. high, low, low, and low. d. disabled due to the circuit pull-ups and to a common connection on the last gate. NOTE: Make sure all CMs are cleared (turned off) before proceeding to the next section. 60 FACET by Lab-Volt
Exercise 2: OR/NOR Logic Functions
Exercise 2: OR/NOR Logic Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the operation of an OR and a NOR logic gate. You will verify your results by generating
Exercise 1: EXCLUSIVE OR/NOR Gate Functions
EXCLUSIVE-OR/NOR Gates Digital Logic Fundamentals Exercise 1: EXCLUSIVE OR/NOR Gate Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the operation of
Exercise 1: DC Operation of a NOT and an OR-TIE
Open Collector and Other TTL Gates Digital Logic Fundamentals Exercise 1: DC Operation of a NOT and an OR-TIE EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the
Exercise 1: Circuit Block Familiarization
Exercise 1: Circuit Block Familiarization EXERCISE OBJECTIVE When you have completed this exercise, you will be able to locate and identify the circuit blocks and components on the DIGITAL LOGIC FUNDAMENTALS
Exercise 2: Current in a Series Resistive Circuit
DC Fundamentals Series Resistive Circuits Exercise 2: Current in a Series Resistive Circuit EXERCISE OBJECTIVE circuit by using a formula. You will verify your results with a multimeter. DISCUSSION Electric
Exercise 1: Tri-State Buffer Output Control
Exercise 1: Tri-State Buffer Output Control EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate how the enable and data inputs control the output state of a tri-state
Exercise 2: Source and Sink Current
Digital Logic Fundamentals Tri-State Output Exercise 2: Source and Sink Current EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate how a tri-state buffer output can
Exercise 1: Inductors
Exercise 1: Inductors EXERCISE OBJECTIVE When you have completed this exercise, you will be able to describe the effect an inductor has on dc and ac circuits by using measured values. You will verify your
TECH 3232 Fall 2010 Lab #1 Into To Digital Circuits. To review basic logic gates and digital logic circuit construction and testing.
TECH 3232 Fall 2010 Lab #1 Into To Digital Circuits Name: Purpose: To review basic logic gates and digital logic circuit construction and testing. Introduction: The most common way to connect circuits
Exercise 3: Voltage in a Series Resistive Circuit
DC Fundamentals Series Resistive Circuits Exercise 3: Voltage in a Series Resistive Circuit EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the voltage in a series
Exercise 3: Ohm s Law Circuit Voltage
Ohm s Law DC Fundamentals Exercise 3: Ohm s Law Circuit Voltage EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine voltage by using Ohm s law. You will verify your
Exercise 2: Ohm s Law Circuit Current
Exercise 2: Circuit Current EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine current by using Ohm s law. You will verify your results with a multimeter. DISCUSSION
Exercise 3: Power in a Series/Parallel Circuit
DC Fundamentals Power in DC Circuits Exercise 3: Power in a Series/Parallel Circuit EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the power dissipated in a series/
Exercise 1: Series RLC Circuits
RLC Circuits AC 2 Fundamentals Exercise 1: Series RLC Circuits EXERCISE OBJECTIVE When you have completed this exercise, you will be able to analyze series RLC circuits by using calculations and measurements.
Exercise 2: Inductors in Series and in Parallel
Exercise 2: Inductors in Series and in Parallel EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the total inductance of a circuit containing inductors in series
Lab 5. Binary Counter
Lab. Binary Counter Overview of this Session In this laboratory, you will learn: Continue to use the scope to characterize frequencies How to count in binary How to use an MC counter Introduction The TA
Schmitt Trigger Inputs, Decoders
Schmitt Trigger, Decoders Page 1 Schmitt Trigger Inputs, Decoders TTL Switching In this lab we study the switching of TTL devices. To do that we begin with a source that is unusual for logic circuits,
Lab 6. Binary Counter
Lab 6. Binary Counter Overview of this Session In this laboratory, you will learn: Continue to use the scope to characterize frequencies How to count in binary How to use an MC14161 or CD40161BE counter
Exercise 2: Temperature Measurement
Exercise 2: Temperature Measurement EXERCISE OBJECTIVE When you have completed this exercise, you will be able to explain the use of a thermocouple in temperature measurement applications. DISCUSSION the
2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.
2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion
In this experiment you will study the characteristics of a CMOS NAND gate.
Introduction Be sure to print a copy of Experiment #12 and bring it with you to lab. There will not be any experiment copies available in the lab. Also bring graph paper (cm cm is best). Purpose In this
UNIVERSITI MALAYSIA PERLIS
UNIVERSITI MALAYSIA PERLIS DIGITAL SYSTEM I (DKT122) LAB 2: LOGIC GATE QUESTION & ANSWER SHEET REPORT MOHAMAD RIZAL BIN ABDUL REJAB SITI ZARINA BINTI MD NAZIRI & SPECIAL THANKS TO : ZULKIFLI HUSIN MOHAMMAD
When you have completed this exercise, you will be able to determine the ac operating characteristics of
When you have completed this exercise, you will be able to determine the ac operating characteristics of multimeter and an oscilloscope. A sine wave generator connected between the transistor and ground
EXPERIMENT 12: DIGITAL LOGIC CIRCUITS
EXPERIMENT 12: DIGITAL LOGIC CIRCUITS The purpose of this experiment is to gain some experience in the use of digital logic circuits. These circuits are used extensively in computers and all types of electronic
The collector terminal is common to the input and output signals and is connected to the dc power supply. Common Collector Circuit
Common Collector Circuit When you have completed this exercise, you will be able to determine the dc operating conditions of a common collector (CC) transistor circuit by using a typical CC circuit. You
Schmitt trigger. V I is converted from a sine wave into a square wave. V O switches between +V SAT SAT and is in phase with V I.
When you have completed this exercise, you will be able to operate a sine wave to square wave converter. You will verify your results with an oscilloscope. Schmitt trigger. V I is converted from a sine
Lab# 13: Introduction to the Digital Logic
Lab# 13: Introduction to the Digital Logic Revision: October 30, 2007 Print Name: Section: In this lab you will become familiar with Physical and Logical Truth tables. As well as asserted high, asserted
Lab Project #2: Small-Scale Integration Logic Circuits
Lab Project #2: Small-Scale Integration Logic Circuits Duration: 2 weeks Weeks of 1/31/05 2/7/05 1 Objectives The objectives of this laboratory project are to design some simple logic circuits using small-scale
Exercise 2: Q and Bandwidth of a Series RLC Circuit
Series Resonance AC 2 Fundamentals Exercise 2: Q and Bandwidth of a Series RLC Circuit EXERCISE OBJECTIVE When you have completed this exercise, you will be able to calculate the bandwidth and Q of a series
Lab 2: Combinational Circuits Design
Lab : Combinational Circuits Design PURPOSE: The purpose of this laboratory assignment is to investigate the design of combinational circuits using SSI circuits and basic logic gates such as ANDs, ORs,
Exercise 2: Temperature Measurement
Exercise 2: Temperature Measurement EXERCISE OBJECTIVE When you have completed this exercise, you will be able to explain and demonstrate the use of an RTD in a temperature measurement application by using
DIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3
DIGITAL ELECTRONICS Marking scheme : Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3 Aim: This experiment will investigate the function of the
Subject: Analog and Digital Electronics Code:15CS32
Subject: Analog and Digital Electronics Code:15CS32 Syllabus: The Basic Gates : Review of Basic Logic gates, Positive and Negative Logic, Introduction to HDL. Combinational Logic Circuits:Sum-of-Products
Exercise 1: The Rheostat
Potentiometers and Rheostats DC Fundamentals Exercise 1: The Rheostat EXERCISE OBJECTIVE When you have completed this exercise, you will be able to vary current by using a rheostat. You will verify your
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true
Experiment # 2 The Voting Machine
Experiment # 2 The Voting Machine 1. Synopsis: In this lab we will build a simple logic circuit of a voting machine using TTL gates using integrated circuits that contain one or more gates packaged inside.
Experiment 5: Basic Digital Logic Circuits
ELEC 2010 Laboratory Manual Experiment 5 In-Lab Procedure Page 1 of 5 Experiment 5: Basic Digital Logic Circuits In-Lab Procedure and Report (30 points) Before starting the procedure, record the table
using dc inputs. You will verify circuit operation with a multimeter.
Op Amp Fundamentals using dc inputs. You will verify circuit operation with a multimeter. FACET by Lab-Volt 77 Op Amp Fundamentals O circuit common. a. inverts the input voltage polarity. b. does not invert
When you have completed this exercise, you will be able to determine ac operating characteristics of a
When you have completed this exercise, you will be able to determine ac operating characteristics of a multimeter and an oscilloscope. A sine wave generator connected between the transistor base and ground
Exercise 2: Parallel RLC Circuits
RLC Circuits AC 2 Fundamentals Exercise 2: Parallel RLC Circuits EXERCSE OBJECTVE When you have completed this exercise, you will be able to analyze parallel RLC circuits by using calculations and measurements.
Name EGR 2131 Lab #2 Logic Gates and Boolean Algebra Objectives Equipment and Components Part 1: Reading Pin Diagrams 7400 (TOP VIEW)
Name EGR 23 Lab #2 Logic Gates and Boolean Algebra Objectives ) Become familiar with common logic-gate chips and their pin numbers. 2) Using breadboarded chips, investigate the behavior of NOT (Inverter),
This Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations.
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 5 Lecture Title:
Java Bread Board Introductory Digital Electronics Exercise 2, Page 1
Java Bread Board Introductory Digital Electronics Exercise 2, Page 1 JBB Excercise 2 The aim of this lab is to demonstrate how basic logic gates can be used to implement simple memory functions, introduce
Exercise 3: EXERCISE OBJECTIVE
Exercise 3: EXERCISE OBJECTIVE voltage equal to double the peak ac input voltage by using a voltage doubler circuit. You will verify your results with a multimeter and an oscilloscope. DISCUSSION times
Exercise 3: Series-Shunt Voltage Gain
Exercise 3: Series-Shunt Voltage Gain When you have completed this exercise, you will be able to calculate and measure series-shunt voltage oscilloscope. Resistor R ef provides series feedback to the input
ENG 100 Electric Circuits and Systems Lab 6: Introduction to Logic Circuits
ENG 100 Electric Circuits and Systems Lab 6: Introduction to Logic Circuits Professor P. Hurst Lecture 5:10p 6:00p TR, Kleiber Hall Lab 2:10p 5:00p F, 2161 Kemper Hall LM741 Operational Amplifier Courtesy
Digital Fundamentals. Lab 4 EX-OR Circuits & Combinational Circuit Design
Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 4 EX-OR Circuits & Combinational Circuit Design
EMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 4: Combinational Logic Circuits. Name: Date:
EXPERIMENT # 4: Combinational Logic Circuits Name: Date: Equipment/Parts Needed: 5V DC Power Supply Digital Trainer (Logic Probe) Breadboard DIP Switch 7400 NAND gate 7402 NOR gate 7404 Inverter 7408 AND
Exercise 1: Touch and Position Sensing
Exercise 1: Touch and Position Sensing EXERCISE OBJECTIVE When you have completed this exercise, you will be able to describe and demonstrate the use of a capacitance sensor as a touch sensor and a position
EECE 143 Lecture 0: Intro to Digital Laboratory
EECE 143 Lecture 0: Intro to Digital Laboratory Syllabus * Class Notes Laboratory Equipment Experiment 0 * Experiment 1 Introduction Instructor Information: Mr. J. Christopher Perez Room: Haggerty Engineering,
Electronics. Digital Electronics
Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital
Exercise 1: Power Division
Power in AC Circuits AC 2 Fundamentals Exercise 1: Power Division EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine ac power division among the components of an RLC
Exercise 1: Inductive Reactance
nductive Reactance Exercise 1: nductive Reactance EERCSE OBJECTE When you have completed this exercise, you will be able to determine inductive reactance ( L ) by using calculated and measured values.
Lab 2 Revisited Exercise
Lab 2 Revisited Exercise +15V 100k 1K 2N2222 Wire up led display Note the ground leads LED orientation 6.091 IAP 2008 Lecture 3 1 Comparator, Oscillator +5 +15 1k 2 V- 7 6 Vin 3 V+ 4 V o Notice that power
Odd-Prime Number Detector The table of minterms is represented. Table 13.1
Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1
Lab Exercise 6: Digital/Analog conversion
Lab Exercise 6: Digital/Analog conversion Introduction In this lab exercise, you will study circuits for analog-to-digital and digital-to-analog conversion Preparation Before arriving at the lab, you should
Exercise 1: Series Resonant Circuits
Series Resonance AC 2 Fundamentals Exercise 1: Series Resonant Circuits EXERCISE OBJECTIVE When you have completed this exercise, you will be able to compute the resonant frequency, total current, and
Exercise 2: High-Pass Filters
Exercise 2: High-Pass Filters EXERCISE OBJECTIVE When you have completed this exercise, you will be able to calculate and measure the cutoff frequencies oscilloscope. DISCUSSION of inductors, capacitors,
Logic Circuit Design
Logic Circuit Design we have studied Truth Tables Logic gates Logic algebra K-maps 1 All these are tools Tools Truth Tables Logic gates Logic algebra K-maps 2 All these are tools Tools Truth Tables Logic
Exercise 1: AC Waveform Generator Familiarization
Exercise 1: AC Waveform Generator Familiarization EXERCISE OBJECTIVE When you have completed this exercise, you will be able to operate an ac waveform generator by using equipment provided. You will verify
Computer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University
Computer Architecture: Part II First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Combinational Circuits Flips Flops Flops Sequential Circuits 204231: Computer
Sequential Logic Circuits
LAB EXERCISE - 5 Page 1 of 6 Exercise 5 Sequential Logic Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of simple sequential logic circuits; - measure
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering. EEC 180A DIGITAL SYSTEMS I Winter 2015
UNIVERSITY OF CALIFORNIA, DAVIS Department of Electrical and Computer Engineering EEC 180A DIGITAL SYSTEMS I Winter 2015 LAB 2: INTRODUCTION TO LAB INSTRUMENTS The purpose of this lab is to introduce the
University of North Carolina-Charlotte Department of Electrical and Computer Engineering ECGR 3157 Electrical Engineering Design II Fall 2013
Exercise 1: PWM Modulator University of North Carolina-Charlotte Department of Electrical and Computer Engineering ECGR 3157 Electrical Engineering Design II Fall 2013 Lab 3: Power-System Components and
An input resistor suppresses noise and stray pickup developed across the high input impedance of the op amp.
When you have completed this exercise, you will be able to operate a voltage follower using dc voltages. You will verify your results with a multimeter. O I The polarity of V O is identical to the polarity
Gates and and Circuits
Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the
Lab 8: SWITCHED CAPACITOR CIRCUITS
ANALOG & TELECOMMUNICATION ELECTRONICS LABORATORY EXERCISE 8 Lab 8: SWITCHED CAPACITOR CIRCUITS Goal The goals of this experiment are: - Verify the operation of basic switched capacitor cells, - Measure
Encoders. Lecture 23 5
-A decoder with enable input can function as a demultiplexer a circuit that receives information from a single line and directs it to one of 2 n possible output lines. The selection of a specific output
EXPERIMENT NO 1 TRUTH TABLE (1)
EPERIMENT NO AIM: To verify the Demorgan s theorems. APPARATUS REQUIRED: THEORY: Digital logic trainer and Patch cords. The digital signals are discrete in nature and can only assume one of the two values
TTL LOGIC and RING OSCILLATOR TTL
ECE 2274 TTL LOGIC and RING OSCILLATOR TTL We will examine two digital logic inverters. The first will have a passive resistor pull-up output stage. The second will have an active transistor and current
EE 2274 DIODE OR GATE & CLIPPING CIRCUIT
EE 2274 DIODE OR GATE & CLIPPING CIRCUIT Prelab Part I: Wired Diode OR Gate LTspice use 1N4002 1. Design a diode OR gate, Figure 1 in which the maximum current thru R1 I R1 = 9mA assume Vin = 5Vdc. Design
This transistor circuit has a voltage divider circuit with an emitter resistor for bias stability.
When you have completed this exercise, you will be able to describe the temperature effects on a voltage divider bias circuit by using a typical transistor circuit. You will verify your results with a
Module -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
Exercise 2: Distance Measurement
Transducer Fundamentals Ultrasonic Transducers Exercise 2: Distance Measurement EXERCISE OBJECTIVE At the completion of this exercise, you will be able to explain and demonstrate the operation of ultrasonic
1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.
Name: Multiple Choice 1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.) 8 2.) The output of an OR gate with
Lab #10: Finite State Machine Design
Lab #10: Finite State Machine Design Zack Mattis Lab: 3/2/17 Report: 3/14/17 Partner: Brendan Schuster Purpose In this lab, a finite state machine was designed and fully implemented onto a protoboard utilizing
Laboratory Manual CS (P) Digital Systems Lab
Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification
Basic Logic Circuits
Basic Logic Circuits Required knowledge Measurement of static characteristics of nonlinear circuits. Measurement of current consumption. Measurement of dynamic properties of electrical circuits. Definitions
Revised: Summer 2010
EE 2274 PRE-LAB EXPERIMENT 5 DIODE OR GATE & CLIPPING CIRCUIT COMPLETE PRIOR TO COMING TO LAB Part I: 1. Design a diode, Figure 1 OR gate in which the maximum input current,, Iin is less than 5mA. Show
EE283 Electrical Measurement Laboratory Laboratory Exercise #7: Digital Counter
EE283 Electrical Measurement Laboratory Laboratory Exercise #7: al Counter Objectives: 1. To familiarize students with sequential digital circuits. 2. To show how digital devices can be used for measurement
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page
UNIT E1 (Paper version of on-screen assessment) A.M. WEDNESDAY, 8 June hour
Candidate Name GCSE 46/0 Centre Number Candidate Number 0 ELECTRONICS UNIT E (Paper version of on-screen assessment) A.M. WEDNESDAY, 8 June 20 hour For s use 46 0000 Total Mark ADDITIONAL MATERIALS Information
Exercise 1: Effect of Shunt Feedback on AC Gain
Exercise 1: Effect of Shunt Feedback on AC Gain When you have completed this exercise, you will be able to understand the effect of shunt negative feedback on ac gain by using a typical shunt feedback
Logic diagram: a graphical representation of a circuit
LOGIC AND GATES Introduction to Logic (1) Logic diagram: a graphical representation of a circuit Each type of gate is represented by a specific graphical symbol Truth table: defines the function of a gate
Logic Families. Describes Process used to implement devices Input and output structure of the device. Four general categories.
Logic Families Characterizing Digital ICs Digital ICs characterized several ways Circuit Complexity Gives measure of number of transistors or gates Within single package Four general categories SSI - Small
Gates and Circuits 1
1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior
DEPARTMENT OF ELECTRICAL ENGINEERING LAB WORK EE301 ELECTRONIC CIRCUITS
DEPARTMENT OF ELECTRICAL ENGINEERING LAB WORK EE301 ELECTRONIC CIRCUITS EXPERIMENT : 3 TITLE : Operational Amplifier (Op-Amp) OUTCOME : Upon completion of this unit, the student should be able to: 1. Gain
Oct 10 & 17 EGR 220: Engineering Circuit Theory Due Oct 17 & 24 Lab 4: Op Amp Circuits
Oct 10 & 17 EGR 220: Engineering Circuit Theory Due Oct 17 & 24 Lab 4: Op Amp Circuits Objective The objective of this lab is to build simple op amp circuits and compare observed behavior with theoretical
CHAPTER 6 DIGITAL INSTRUMENTS
CHAPTER 6 DIGITAL INSTRUMENTS 1 LECTURE CONTENTS 6.1 Logic Gates 6.2 Digital Instruments 6.3 Analog to Digital Converter 6.4 Electronic Counter 6.6 Digital Multimeters 2 6.1 Logic Gates 3 AND Gate The
EXPERIMENT 1 PRELIMINARY MATERIAL
EXPERIMENT 1 PRELIMINARY MATERIAL BREADBOARD A solderless breadboard, like the basic model in Figure 1, consists of a series of square holes, and those columns of holes are connected to each other via
Practical Workbook Logic Design & Switching Theory
Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering
When you have completed this exercise, you will be able to determine the frequency response of an
RC Coupling When you have completed this exercise, you will be able to determine the frequency response of an oscilloscope. The way in which the gain varies with frequency is called the frequency response.
Chapter 3 Describing Logic Circuits Dr. Xu
Chapter 3 Describing Logic Circuits Dr. Xu Chapter 3 Objectives Selected areas covered in this chapter: Operation of truth tables for AND, NAND, OR, and NOR gates, and the NOT (INVERTER) circuit. Boolean
When you have completed this exercise, you will be able to relate the gain and bandwidth of an op amp
Op Amp Fundamentals When you have completed this exercise, you will be able to relate the gain and bandwidth of an op amp In general, the parameters are interactive. However, in this unit, circuit input
DARSHAN INSTITUTE OF ENGINEERING & TECHNOLOGY
BASIC ELECTRONICS (2006) Assignment:-: Circuit Concept. Explain in brief about Lumped circuit elements called resistor and capacitor. 2. How does a voltmeter differ from an ammeter? 3. State kirchhoff's
Exercise 2: AC Voltage and Power Gains
Exercise 2: AC Voltage and Power Gains When you have completed this exercise, you will be able to determine voltage and power gains by using oscilloscope. The ac operation schematic for the COMPLEMENTARY
GCSE (9-1) WJEC Eduqas GCSE (9-1) in ELECTRONICS ACCREDITED BY OFQUAL DESIGNATED BY QUALIFICATIONS WALES SAMPLE ASSESSMENT MATERIALS
GCSE (9-1) WJEC Eduqas GCSE (9-1) in ELECTRONICS ACCREDITED BY OFQUAL DESIGNATED BY QUALIFICATIONS WALES SAMPLE ASSESSMENT MATERIALS Teaching from 2017 For award from 2019 GCSE ELECTRONICS Sample Assessment
E85: Digital Design and Computer Architecture
E85: Digital Design and Computer Architecture Lab 1: Electrical Characteristics of Logic Gates Objective The purpose of this lab is to become comfortable with logic gates as physical objects, to interpret
Exercise 2: FM Detection With a PLL
Phase-Locked Loop Analog Communications Exercise 2: FM Detection With a PLL EXERCISE OBJECTIVE When you have completed this exercise, you will be able to explain how the phase detector s input frequencies
Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405
Digital Applications () Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering systems,