Digital Fundamentals
|
|
- Millicent Mason
- 5 years ago
- Views:
Transcription
1 Digital Fundamentals Tenth Edition Floyd Chapter 3 28 Pearson Education 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
2 The Inverter The inverter performs the oolean NOT operation. When the input is LOW, the output is HIGH; when the input is HIGH, the output is LOW. Input Output LOW () HIGH () HIGH () LOW() The NOT operation (complement) is shown with an overbar. Thus, the oolean expression for an inverter is =. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
3 The Inverter Example waveforms: group of inverters can be used to form the s complement of a binary number: inary number s complement 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
4 The ND Gate & The ND gate produces a HIGH output when all inputs are HIGH; otherwise, the output is LOW. For a 2-input gate, the truth table is Inputs Output The ND operation is usually shown with a dot between the variables but it may be implied (no dot). Thus, the ND operation is written as =. or =. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
5 The ND Gate & Example waveforms: The ND operation is used in computer programming as a selective mask. If you want to retain certain bits of a binary number but reset the other bits to, you could set a mask with s in the position of the retained bits. If the binary number is NDed with the mask, what is the result? 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
6 The ND Gate Multisim circuit is shown. WG is a word generator set in the count down mode. L is a logic analyzer with the output of the ND gate connected to first (upper) line of the analyzer. What signal do you expect to on this line? The output (line ) will be HIGH only when all of the inputs are HIGH. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
7 The OR Gate The OR gate produces a HIGH output if any input is HIGH; if all inputs are LOW, the output is LOW. For a 2-input gate, the truth table is Inputs Output The OR operation is shown with a plus sign (+) between the variables. Thus, the OR operation is written as = Pearson Education, Upper Saddle River, NJ ll Rights Reserved
8 The OR Gate Example waveforms: The OR operation can be used in computer programming to set certain bits of a binary number to. SCII letters have a in the bit 5 position for lower case letters and a in this position for capitals. (it positions are numbered from right to left starting with.) What will be the result if you OR an SCII letter with the 8-bit mask? The resulting letter will be lower case. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
9 The OR Gate Multisim circuit is shown. WG is a word generator set to count down. L is a logic analyzer with the output connected to first (top) line of the analyzer. The three 2-input OR gates act as a single 4-input gate. What signal do you expect on the output line? The output (line ) will be HIGH if any input is HIGH; otherwise it will be LOW. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
10 The NND Gate & The NND gate produces a LOW output when all inputs are HIGH; otherwise, the output is HIGH. For a 2-input gate, the truth table is Inputs Output The NND operation is shown with a dot between the variables and an overbar covering them. Thus, the NND operation is written as =. (lternatively, =.) 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
11 The NND Gate & Example waveforms: The NND gate is particularly useful because it is a universal gate all other basic gates can be constructed from NND gates. How would you connect a 2-input NND gate to form a basic inverter? 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
12 The NND Gate Multisim circuit is shown. WG is a word generator set in the count up mode. four-channel oscilloscope monitors the inputs and output. What output signal do you expect to see? The output (channel D) will be LOW only when all of the inputs are HIGH. Inputs 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
13 The NOR Gate The NOR gate produces a LOW output if any input is HIGH; if all inputs are HIGH, the output is LOW. For a 2-input gate, the truth table is Inputs Output The NOR operation is shown with a plus sign (+) between the variables and an overbar covering them. Thus, the NOR operation is written as = Pearson Education, Upper Saddle River, NJ ll Rights Reserved
14 The NOR Gate Example waveforms: The NOR operation will produce a LOW if any input is HIGH. +5. V When is the LED is ON for the circuit shown? The LED will be on when any of the four inputs are HIGH. C D 33 W 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
15 The OR Gate = The OR gate produces a HIGH output only when both inputs are at opposite logic levels. The truth table is Inputs Output The OR operation is written as = +. lternatively, it can be written with a circled plus sign between the variables as = Pearson Education, Upper Saddle River, NJ ll Rights Reserved
16 The OR Gate = Example waveforms: Notice that the OR gate will produce a HIGH only when exactly one input is HIGH. If the and waveforms are both inverted for the above waveforms, how is the output affected? There is no change in the output. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
17 The NOR Gate = The NOR gate produces a HIGH output only when both inputs are at the same logic level. The truth table is Inputs Output The NOR operation shown as = +. lternatively, the NOR operation can be shown with a circled dot between the variables. Thus, it can be shown as =.. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
18 The NOR Gate = Example waveforms: Notice that the NOR gate will produce a HIGH when both inputs are the same. This makes it useful for comparison functions. If the waveform is inverted but remains the same, how is the output affected? The output will be inverted. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
19 Fixed Function Logic Two major fixed function logic families are TTL and CMOS. third technology is icmos, which combines the first two. Packaging for fixed function logic is shown in in in. 7 Pin no. identifiers ±. in Lead no. identifier 4 4 DIP package SOIC package 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
20 Fixed Function Logic Some common gate configurations are shown. VCC VCC ' 8 7 GND VCC ' 8 7 GND VCC ' 2 7 GND ' GND ' '4 8 7 GND 8 7 GND ' GND ' '8 8 7 GND 8 7 GND '2 8 7 GND VCC VCC VCC VCC VCC VCC VCC VCC ' GND ' GND 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
21 Fixed Function Logic Logic symbols show the gates and associated pin numbers. VCC (4) () (3) (2) (4) (6) (5) (9) (8) () (2) () (3) () (2) (4) (5) (9) () (2) (3) & (3) (6) (8) () (7) GND 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
22 Fixed Function Logic Data sheets include limits and conditions set by the manufacturer as well as DC and C characteristics. For example, some maximum ratings for a 74HC are: MIMUM RTINGS Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND).5 to + 7. V V V in DC InputVoltage (Referenced to GND).5 to VCC +.5 V V V out DC Output Voltage (Referenced to GND).5 to VCC +.5 V V I in DC Input Current, per pin ± 2 m Iout DC Output Current, per pin ± 25 m ICC DC Supply Current, VCC and GND pins ± 5 m PD Power Dissipation in Still ir, Plastic or Ceramic DIP 75 mw 5 SOIC Package TSSOP Package 45 Tstg Storage Temperature 65 to + 5 C TL Lead Temperature, mm from Case for Seconds C 26 Plastic DIP, SOIC, or TSSOP Package 3 Ceramic DIP 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
23 Programmable Logic Programmable Logic Device (PLD) can be programmed to implement logic. There are various technologies available for PLDs. Many use an internal array of ND gates to form logic terms. Many PLDs can be programmed multiple times. SRM cell SRM cell SRM cell SRM cell SRM cell SRM cell SRM cell SRM cell = 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
24 Programmable Logic In general, the required logic for a PLD is developed with the aid of a computer. The logic can be entered using a Hardware Description Language (HDL) such as VHDL. Logic can be specified to the HDL as a text file, a schematic diagram, or a state diagram. text entry for a programming a PLD in VHDL as a 2-input NND gate is shown for reference in the following slide. In this case, the inputs and outputs are first specified. Then the signals are described. lthough you are probably not familiar with VHDL, you can see that the program is simple to read. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
25 Programmable Logic entity NandGate is port(, : in bit; LED: out bit); end entity NandGate; architecture Gateehavior of NandGate is signal, : bit; begin <= nand ; LED <= ; end architecture Gateehavior; 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
26 Selected Key Terms Inverter logic circuit that inverts or complements its inputs. Truth table table showing the inputs and corresponding output(s) of a logic circuit. Timing diagram of waveforms showing the proper time diagram relationship of all of the waveforms. oolean The mathematics of logic circuits. algebra ND gate logic gate that produces a HIGH output only when all of its inputs are HIGH. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
27 Selected Key Terms OR gate logic gate that produces a HIGH output when one or more inputs are HIGH. NND gate logic gate that produces a LOW output only when all of its inputs are HIGH. NOR gate logic gate that produces a LOW output when one or more inputs are HIGH. Exclusive OR logic gate that produces a HIGH output only gate when its two inputs are at opposite levels. Exclusive NOR logic gate that produces a LOW output only gate when its two inputs are at opposite levels. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
28 . The truth table for a 2-input ND gate is Inputs a. Inputs c. Output Inputs b. Output Output Inputs Output d. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
29 2. The truth table for a 2-input NOR gate is Inputs a. Inputs c. Output Inputs b. Output Output Inputs Output d. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
30 3. The truth table for a 2-input OR gate is Inputs a. Inputs c. Output Inputs b. Output Output Inputs Output d. 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
31 4. The symbol is for a(n) a. OR gate b. ND gate c. NOR gate d. OR gate 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
32 5. The symbol is for a(n) a. OR gate b. ND gate c. NOR gate d. OR gate 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
33 6. logic gate that produces a HIGH output only when all of its inputs are HIGH is a(n) a. OR gate b. ND gate c. NOR gate d. NND gate 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
34 7. The expression = + means a. OR b. ND c. OR d. NOR 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
35 8. 2-input gate produces the output shown. ( represents the output.) This is a(n) a. OR gate b. ND gate c. NOR gate d. NND gate 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
36 9. 2-input gate produces a HIGH output only when the inputs agree. This type of gate is a(n) a. OR gate b. ND gate c. NOR gate d. NOR gate 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
37 . The required logic for a PLD can be specified in an Hardware Description Language by a. text entry b. schematic entry c. state diagrams d. all of the above 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved 28 Pearson Education
38 nswers:. c 6. b 2. b 7. c 3. a 8. d 4. a 9. d 5. d. d 29 Pearson Education, Upper Saddle River, NJ ll Rights Reserved
Digital Fundamentals 9/4/2017. Summary. Summary. Floyd. Chapter 3. The Inverter
Digital Fundamentals Tenth Edition Floyd Chapter 3 29 Pearson Education, Upper 28 Pearson Saddle River, Education NJ 7458. ll Rights Reserved The Inverter The inverter performs the oolean NOT operation.
More informationDigital Fundamentals 8/29/2016. Summary. Summary. Floyd. Chapter 3 A X. The Inverter
Digital Fundamentals Tenth Edition Floyd Chapter 3 The Inverter The inverter performs the oolean NOT operation. When the input is LOW, the output is HIGH; when the input is HIGH, the output is LOW. Input
More informationDigital Fundamentals
07/ago/2017 Digital Fundamentals ELEVENTH EDITION CHPTER 1 Introductory Concepts Digital electronics uses circuits that have two states, which are represented by two different voltage levels called HIGH
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd hapter 5 Floyd, Digital Fundamentals, th ed 28 Pearson Education 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved ombinational Logic ircuits
More informationDigital Fundamentals A Systems Approach Thomas L. Floyd First Edition
Digital Fundamentals Systems pproach Thomas L. Floyd First Edition Pearson Education Limited Edinburgh Gate Harlow Essex M20 2JE England and ssociated ompanies throughout the world Visit us on the World
More informationThis Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations.
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 5 Lecture Title:
More information2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.
2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion
More informationChapter 3 Describing Logic Circuits Dr. Xu
Chapter 3 Describing Logic Circuits Dr. Xu Chapter 3 Objectives Selected areas covered in this chapter: Operation of truth tables for AND, NAND, OR, and NOR gates, and the NOT (INVERTER) circuit. Boolean
More informationChapter 4 Combinational Logic Circuits
Chapter 4 Combinational Logic Circuits Chapter 4 Objectives Selected areas covered in this chapter: Converting logic expressions to sum-of-products expressions. Boolean algebra and the Karnaugh map as
More informationPhilips Semiconductors Programmable Logic Devices
DESCRIPTION The PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce maximum propagation
More informationGates and Circuits 1
1 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the behavior
More informationIn this lecture: Lecture 8: ROM & Programmable Logic Devices
In this lecture: Lecture 8: ROM Programmable Logic Devices Dr Pete Sedcole Department of EE Engineering Imperial College London http://caseeicacuk/~nps/ (Floyd, 3 5, 3) (Tocci 2, 24, 25, 27, 28, 3 34)
More informationAppendix B Page 1 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN ASSIGNMENT (TOP VIEWS)
Appendix B Page 1 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN ASSIGNMENT (TOP VIEWS) See page 3 See page 3 See page 7 See page 14 See page 9 See page 16 See page 10 TEXAS INSTRUMENTS LTD have given their
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd Chapter 1 2009 Pearson Education, Upper 2008 Pearson Saddle River, Education NJ 07458. All Rights Reserved Objectives After completing this unit, you should be
More informationPresettable Counter High-Speed Silicon-Gate CMOS
TECHNICAL DATA IN74AC161 Presettable Counter High-Speed Silicon-Gate CMOS The IN74AC161 is identical in pinout to the LS/ALS161, HC/HCT161. The device inputs are compatible with standard CMOS outputs;
More informationChapter 4 Combinational Logic Circuits
Chapter 4 Combinational Logic Circuits Chapter 4 Objectives Selected areas covered in this chapter: Converting logic expressions to sum-of-products expressions. Boolean algebra and the Karnaugh map as
More informationName EGR 2131 Lab #2 Logic Gates and Boolean Algebra Objectives Equipment and Components Part 1: Reading Pin Diagrams 7400 (TOP VIEW)
Name EGR 23 Lab #2 Logic Gates and Boolean Algebra Objectives ) Become familiar with common logic-gate chips and their pin numbers. 2) Using breadboarded chips, investigate the behavior of NOT (Inverter),
More informationLSN 3 Logic Gates. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 3 Logic Gates Department of Engineering Technology LSN 3 Inverter One input and one output Produces a compliment of the input Negation indicator Truth table Active low output In Out 0 1 1 0 Active
More informationLecture 2: Digital Logic Basis
Lecture 2: Digital Logic Basis Xufeng Kou School of Information Science and Technology ShanghaiTech University 1 Outline Truth Table Basic Logic Operation and Gates Logic Circuits NOR Gates and NAND Gates
More informationDepartment of EECS. University of California, Berkeley. Logic gates. September 1 st 2001
Department of EECS University of California, Berkeley Logic gates Bharathwaj Muthuswamy and W. G. Oldham September 1 st 2001 1. Introduction This lab introduces digital logic. You use commercially available
More informationTECH 3232 Fall 2010 Lab #1 Into To Digital Circuits. To review basic logic gates and digital logic circuit construction and testing.
TECH 3232 Fall 2010 Lab #1 Into To Digital Circuits Name: Purpose: To review basic logic gates and digital logic circuit construction and testing. Introduction: The most common way to connect circuits
More informationLab# 13: Introduction to the Digital Logic
Lab# 13: Introduction to the Digital Logic Revision: October 30, 2007 Print Name: Section: In this lab you will become familiar with Physical and Logical Truth tables. As well as asserted high, asserted
More informationDO NOT COPY DO NOT COPY
18 Chapter 1 Introduction 1.9 Printed-Circuit oards printed-circuit board n IC is normally mounted on a printed-circuit board (PC) [or printed-wiring (PC) board (PW)] that connects it to other ICs in a
More informationAim. Lecture 1: Overview Digital Concepts. Objectives. 15 Lectures
Aim Lecture 1: Overview Digital Concepts to give a first course in digital electronics providing you with both the knowledge and skills required to design simple digital circuits and preparing you for
More informationECE380 Digital Logic
ECE380 Digital Logic Implementation Technology: Standard Chips and Programmable Logic Devices Dr. D. J. Jackson Lecture 10-1 Standard chips A number of chips, each with a few logic gates, are commonly
More informationQuad 2-Input NAND Gate High-Voltage Silicon-Gate CMOS
TECHNICAL DATA Quad 2-Input NAND Gate High-oltage Silicon-Gate CMOS The NAND gates provide the system designer with direct emplementation of the NAND function. Operating oltage Range:.0 to 18 Maximum input
More informationOctal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HCT573A Octal 3-State Noninverting Transparent Latch High-Performance Silicon-Gate CMOS The IN74HCT573A is identical in pinout to the LS/ALS573. This device may be used as a level converter
More informationDigital Fundamentals. Logic gates
Digital Fundamentals Logic gates Objectives Describe the operation of the inverter, the AND gate, and the OR gate Describe the operation of the NAND gate and the NOR gate Express the operation of the NOT,
More informationCode No: R Set No. 1
Code No: R05310402 Set No. 1 1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate. (b) Design a CMOS
More informationGates and and Circuits
Chapter 4 Gates and Circuits Chapter Goals Identify the basic gates and describe the behavior of each Describe how gates are implemented using transistors Combine basic gates into circuits Describe the
More informationMM74HCU04 Hex Inverter
MM74HCU04 Hex Inverter General Description The MM74HCU04 inverters utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
More informationIn this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions
In this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions Dr Pete Sedcole Department of E&E Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/ (Floyd 3.1 3.6, 4.1) (Tocci 3.1 3.9)
More informationDigital Logic Circuits
Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals
More informationPresettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS
TECHNICAL DATA Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS IN74ACT193 The IN74ACT193 is identical in pinout to the LS/ALS192, HC/HCT192. The IN74ACT193 may be used as a level
More informationPREVIEW COPY. Digital Logic Systems. Table of Contents. Digital Logic Fundamentals...3. Logic Building Blocks Medium- and Large-Scale ICs...
Digital Logic Systems Table of Contents Lesson One Lesson Two Lesson Three Digital Logic Fundamentals...3 Logic uilding locks...9 Medium- and Large-Scale ICs...35 Lesson Four Functional Logic Systems...5
More informationDigital Fundamentals. Introductory Digital Concepts
Digital Fundamentals Introductory Digital Concepts Objectives Explain the basic differences between digital and analog quantities Show how voltage levels are used to represent digital quantities Describe
More informationMM74HC132 Quad 2-Input NAND Schmitt Trigger
Quad 2-Input NAND Schmitt Trigger General Description The utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well as the capability
More information16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154)
16 Multiplexers and De-multiplexers using gates and ICs. (74150, 74154) Aim: To design multiplexers and De-multiplexers using gates and ICs. (74150, 74154) Components required: Digital IC Trainer kit,
More informationPresettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS
TECHNICAL DATA Presettable 4-Bit Binary UP/DOWN Counter High-Speed Silicon-Gate CMOS IN74AC193 The IN74AC193 is identical in pinout to the LS/ALS193, HC/HCT193. The device inputs are compatible with standard
More informationCourse Outline Cover Page
College of Micronesia FSM P.O. Box 159 Kolonia, Pohnpei Course Outline Cover Page Digital Electronics I VEE 135 Course Title Department and Number Course Description: This course provides the students
More informationAnalysis procedure. To obtain the output Boolean functions from a logic diagram, proceed as follows:
Combinational Logic Logic circuits for digital systems may be combinational or sequential. combinational circuit consists of input variables, logic gates, and output variables. 1 nalysis procedure To obtain
More informationEngr354: Digital Logic Circuits
Engr354: Digital Logic Circuits Chapter 3: Implementation Technology Curtis Nelson Chapter 3 Overview In this chapter you will learn about: How transistors are used as switches; Integrated circuit technology;
More informationLogic Symbols with Truth Tables INVERTER A B NAND A B C NOR C A B A B C XNOR A B C A B Digital Logic 1
Slide Logic Symbols with Truth Tables UFFER INVERTER ND NND OR NOR XOR XNOR 6.7 Digital Logic Digital logic can be described in terms of standard logic symbols and their corresponding truth tables. The
More informationDIGITAL ELECTRONICS: LOGIC AND CLOCKS
DIGITL ELECTRONICS: LOGIC ND CLOCKS L 9 INTRO: INTRODUCTION TO DISCRETE DIGITL LOGIC, MEMORY, ND CLOCKS GOLS In this experiment, we will learn about the most basic elements of digital electronics, from
More informationDigital Systems Principles and Applications TWELFTH EDITION. 3-3 OR Operation With OR Gates. 3-4 AND Operations with AND gates
Digital Systems Principles and Applications TWELFTH EDITION CHAPTER 3 Describing Logic Circuits Part -2 J. Bernardini 3-3 OR Operation With OR Gates An OR gate is a circuit with two or more inputs, whose
More informationEE40 Lecture 35. Prof. Chang-Hasnain. 12/5/07 Reading: Ch 7, Supplementary Reader
EE4 Lecture 35 2/5/7 Reading: Ch 7, Supplementary Reader EE4 all 26 Slide Week 5 OUTLINE Need for Input Controlled Pull-Up CMOS Inverter nalysis CMOS Voltage Transfer Characteristic Combinatorial logic
More informationM74HCT164TTR 8 BIT SIPO SHIFT REGISTER
8 BIT SIPO SHIFT REGISTER HIGH SPEED: t PD = 24 ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) BALANCED PROPAGATION
More informationEE100Su08 Lecture #16 (August 1 st 2008)
EESu8 Lecture #6 (ugust st 28) OUTLINE Project next week: Pick up kits in your first lab section, work on the project in your first lab section, at home etc. and wrap up in the second lab section. USE
More informationMM74HC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard
More informationDigital Circuits Introduction
Lecture #6 OUTLINE Logic inary representations Combinatorial logic circuits Chap 7-7.5 Reading EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu Digital Circuits Introduction nalog: signal amplitude
More informationDr. Cahit Karakuş ANALOG SİNYALLER
Dr. Cahit Karakuş ANALOG SİNYALLER Sinusoidal Waveform Mathematically it is represented as: Sinusoidal Waveform Unit of measurement for horizontal axis can be time, degrees or radians. Sinusoidal Waveform
More informationMM74HC132 Quad 2-Input NAND Schmitt Trigger
Quad 2-Input NAND Schmitt Trigger General Description The MM74HC132 utilizes advanced silicon-gate CMOS technology to achieve the low power dissipation and high noise immunity of standard CMOS, as well
More information. HIGH SPEED .LOW POWER DISSIPATION .COMPATIBLE WITH TTL OUTPUTS M54HCT30 M74HCT30 8 INPUT NAND GATE. tpd = 15 ns (TYP.
M54HCT30 M74HCT30 8 INPUT NAND GATE. HIGH SPEED tpd = 15 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =1µA (MAX.) AT T A =25 C.COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) OUTPUT DRIVE
More informationUnit level 4 Credit value 15. Introduction. Learning Outcomes
Unit 20: Unit code Digital Principles T/615/1494 Unit level 4 Credit value 15 Introduction While the broad field of electronics covers many aspects, it is digital electronics which now has the greatest
More informationPositive and Negative Logic
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 4 Lecture Title:
More informationDIGITAL FUNDAMENTALS
Instructor s Resource Manual to accompany DIGITAL FUNDAMENTALS Ninth Edition Thomas L. Floyd Upper Saddle River, New Jersey Columbus, Ohio Copyright 26 by Pearson Education, Inc., Upper Saddle River, New
More informationName: Class: Date: 1. As more electronic systems have been designed using digital technology, devices have become smaller and less powerful.
Name: Class: Date: DE Midterm Review 2 True/False Indicate whether the statement is true or false. 1. As more electronic systems have been designed using digital technology, devices have become smaller
More informationAnalog, Digital, and Logic
Analog, Digital, and Logic Analog and Digital A/D and D/A conversion Prof Carruthers (ECE @ BU) EK307 Notes Summer 2018 116 / 264 Analog and Digital Digital and Analog There are 10 kinds of people: those
More informationNOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package.
DECADE COUNTER; 4-BIT BINARY COUNTER The SN54/ and SN54/ are high-speed 4-bit ripple type counters partitioned into two sectio. Each counter has a divide-by-two section and either a divide-by-five () or
More informationLecture #1. Course Overview
Lecture #1 OUTLINE Course overview Introduction: integrated circuits Analog vs. digital signals Lecture 1, Slide 1 Course Overview EECS 40: One of five EECS core courses (with 20, 61A, 61B, and 61C) introduces
More information1. What is the major problem associated with cascading pass transistor logic gates?
EE 434 Exam 2 Fall 2003 Name Instructions. Students may bring 4 pages of notes to this exam. There are 9 questions. The first 8 are worth 2 points each and question 9 is worth 4 points. There are 6 problems.
More informationCONTENTS Sl. No. Experiment Page No
CONTENTS Sl. No. Experiment Page No 1a Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC. 2a 3a 4a 5a 6a 1b
More informationLogic Design I (17.341) Fall Lecture Outline
Logic Design I (17.341) Fall 2011 Lecture Outline Class # 07 October 31, 2011 / November 07, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative
More informationDigital Fundamentals 8/25/2016. Summary. Summary. Floyd. Chapter 1. Analog Quantities
8/25/206 Digital Fundamentals Tenth Edition Floyd Chapter Analog Quantities Most natural quantities that we see are analog and vary continuously. Analog systems can generally handle higher power than digital
More informationDigital Logic ircuits Circuits Fundamentals I Fundamentals I
Digital Logic Circuits Fundamentals I Fundamentals I 1 Digital and Analog Quantities Electronic circuits can be divided into two categories. Digital Electronics : deals with discrete values (= sampled
More informationPropagation Delay, Circuit Timing & Adder Design. ECE 152A Winter 2012
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationPropagation Delay, Circuit Timing & Adder Design
Propagation Delay, Circuit Timing & Adder Design ECE 152A Winter 2012 Reading Assignment Brown and Vranesic 2 Introduction to Logic Circuits 2.9 Introduction to CAD Tools 2.9.1 Design Entry 2.9.2 Synthesis
More informationSingle supply logic gates with voltage translation
7LVT - 7LVT - 7LVT - 7LVT8-7LVT - 7LVT - 7LVT86-7LVT87-7LVT - 7LVT6 Single supply logic gates with voltage translation Our 7LVTxxx logic family provides solutions that integrate voltage level translation
More informationQuad 2-Input Data Selectors/Multiplexer
TECNICAL DATA IN74C157A Quad 2-Input Data Selectors/Multiplexer The IN74C157A is identical in pin out to the LS/ALS157. The device inputs are compatible with standard CMOS outputs; with pull up resistors,
More informationHigh Performance Silicon Gate CMOS
High Performance Silicon Gate CMOS The MC74CA is identical in pinout to the standard CMOS MC. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with
More informationMultiple input gates. The AND gate
Multiple input gates Inverters and buffers exhaust the possibilities for single-input gate circuits. What more can be done with a single logic signal but to buffer it or invert it? To explore more logic
More informationChapter 4 Logic Functions and Gates
Chapter 4 Logic Functions and Gates CHPTER OJECTIVES Upon successful completion of this chapter, you will be able to: Describe the basic logic functions: ND, OR, and NOT. Draw simple switch circuits to
More informationINTEGRATED CIRCUITS. 74LVC00A Quad 2-input NAND gate. Product specification Supersedes data of 1997 Aug 11 IC24 Data Handbook.
INTEGRATED CIRCUITS Supersedes data of 1997 Aug 11 IC24 Data Handbook 1998 Apr 28 FEATURES Wide supply range of 1.2V to 3.6V Complies with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5V CMOS
More informationLogic diagram: a graphical representation of a circuit
LOGIC AND GATES Introduction to Logic (1) Logic diagram: a graphical representation of a circuit Each type of gate is represented by a specific graphical symbol Truth table: defines the function of a gate
More informationMM74HC00 Quad 2-Input NAND Gate
MM74HC00 Quad 2-Input NAND Gate Features Typical propagation delay: 8 Wide power supply range: 2 6 Low quiescent current: 20µA maximum (74HC Series) Low input current: 1µA maximum Fanout of 10 LS-TTL loads
More informationChapter # 1: Introduction
Chapter # : Randy H. Katz University of California, erkeley May 993 ฉ R.H. Katz Transparency No. - The Elements of Modern Design Representations, Circuit Technologies, Rapid Prototyping ehaviors locks
More information54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
More information. HIGH SPEED .LOW POWER DISSIPATION .COMPATIBLE WITH TTL OUTPUTS M54/74HCT245/640/643 M54/74HCT245/640/643
M54/74HCT245/640/643 M54/74HCT245/640/643 OCTAL BUS TRANSCEIVER (3-STATE): HCT245 NON INVERTING HCT640 INVERTING, HCT643 INVERTING/NON INVERTING. HIGH SPEED t PD = 10 ns (TYP.) at V CC =5V.LOW POWER DISSIPATION
More informationCombinational Circuits: Multiplexers, Decoders, Programmable Logic Devices
Combinational Circuits: Multiplexers, Decoders, Programmable Logic Devices Lecture 5 Doru Todinca Textbook This chapter is based on the book [RothKinney]: Charles H. Roth, Larry L. Kinney, Fundamentals
More informationObsolete Product(s) - Obsolete Product(s)
QUAD 2-INPUT NAND GATE HIGH SPEED: t PD = 12ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) BALANCED PROPAGATION
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC155 M74HC155 DUAL 2 TO 4 LINE DECODER 3 TO 8 LINE DECODER. tpd = 12 ns (TYP.
M54HC155 M74HC155 DUAL 2 TO 4 LINE DECODER 3 TO 8 LINE DECODER. HIGH SPEED tpd = 12 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.)
More informationM74HC4049TTR HEX BUFFER/CONVERTER (INVERTER)
HEX BUFFER/CONVERTER (INVERTER) HIGH SPEED: t PD = 8ns (TYP.) at V CC =6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationDigital Electronic Concepts
Western Technical College 10662137 Digital Electronic Concepts Course Outcome Summary Course Information Description Career Cluster Instructional Level Total Credits 4.00 Total Hours 108.00 This course
More informationDECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C64 8K x 8 LOW POR CMOS STATIC RAM FEATURES CMOS low power operation 400 mw (max.) operating 25 mw (max.) standby Automatic power-down when chip is deselected TTL compatible interface levels Single
More informationCS302 - Digital Logic Design Glossary By
CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital
More informationDATASHEET HI-201HS. Features. Applications. Ordering Information. Pinout (Switches Shown For Logic 1 Input) High Speed, Quad SPST, CMOS Analog Switch
DATASHEET HI-21HS High Speed, Quad SPST, CMOS Analog Switch The HI-21HS is a monolithic CMOS Analog Switch featuring very fast switching speeds and low ON resistance. The integrated circuit consists of
More informationJava Bread Board Introductory Digital Electronics Exercise 2, Page 1
Java Bread Board Introductory Digital Electronics Exercise 2, Page 1 JBB Excercise 2 The aim of this lab is to demonstrate how basic logic gates can be used to implement simple memory functions, introduce
More informationObsolete Product(s) - Obsolete Product(s)
7 STAGE BINARY COUNTER HIGH SPEED : f MAX = 79 MHz (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
More informationObsolete Product(s) - Obsolete Product(s)
OCTAL BUS TRANSCEIVER WITH 3 STATE OUTPUTS (INVERTED) HIGH SPEED: t PD = 13ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V
More informationM74HCT174TTR HEX D-TYPE FLIP FLOP WITH CLEAR
HEX D-TYPE FLIP FLOP WITH CLEAR HIGH SPEED : f MAX = 56MHz (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC =4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
More informationA B. 1 (a) (i) Fig shows the symbol for a circuit component. Fig Name this component. ... [1]
(a) (i) Fig.. shows the symbol for a circuit component. Fig.. Name this component.... [] (ii) In the space below, draw the symbol for a NOT gate. (b) Fig..2 shows a digital circuit. [] C D E Fig..2 Complete
More informationUNIVERSITI MALAYSIA PERLIS
UNIVERSITI MALAYSIA PERLIS DIGITAL SYSTEM I (DKT122) LAB 2: LOGIC GATE QUESTION & ANSWER SHEET REPORT MOHAMAD RIZAL BIN ABDUL REJAB SITI ZARINA BINTI MD NAZIRI & SPECIAL THANKS TO : ZULKIFLI HUSIN MOHAMMAD
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54/74HC374 M54/74HC534
M54/74HC374 M54/74HC534 OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUT HC374 NON INVERTING - HC534 INVERTING. HIGH SPEED f MAX = 77 MHz (TYP.) AT V CC =5V.LOW POWER DISSIPATION ICC =4µA (MAX.) AT TA =25 C.HIGH
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC51 M74HC51 DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE. tpd = 10 ns (TYP.
M54HC51 M74HC51 DUAL 2 WIDE 2 INPUT AND/OR INVERT GATE. HIGH SPEED tpd = 10 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =1µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUT
More informationM74HCT241B1R 74HCT241 OCTAL TRI-STATE BUFFER (DIL20) M74HCT244B1R 74HCT244 OCTAL TRI-STATE BUFFER (DIL20)
DATA SHEET Order code Manufacturer code Description 83-0030 M74HCT241B1R 74HCT241 OCTAL TRI-STATE BUFFER (DIL20) 83-0032 M74HCT244B1R 74HCT244 OCTAL TRI-STATE BUFFER (DIL20) The enclosed information is
More information. HIGH SPEED .LOW POWER DISSIPATION .COMPATIBLE WITH TTL OUTPUTS M54HCT139 M74HCT139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER. tpd = 17 ns (TYP.
M54HCT139 M74HCT139 DUAL 2 TO 4 DECODER/DEMULTIPLEXER. HIGH SPEED tpd = 17 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =4µA (MAX.) AT T A =25 C.COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V
More information. HIGH SPEED .LOW POWER DISSIPATION .HIGH NOISE IMMUNITY M54HC00 M74HC00 QUAD 2-INPUT NAND GATE. tpd = 6 ns (TYP.) AT VCC =5V
M54HC00 M74HC00 QUAD 2-INPUT NAND GATE. HIGH SPEED tpd = 6 ns (TYP.) AT VCC =5V.LOW POWER DISSIPATION I CC =1µA (MAX.) AT T A =25 C.HIGH NOISE IMMUNITY VNIH =VNIL =28%VCC (MIN.) OUTPUTS DRIVE CAPABILITY
More informationDigital Fundamentals
Digital Fundamentals Tenth Edition Floyd Chapter 6 组合逻辑电路函数 Floyd, Digital Fundamentals, th ed 29 Pearson Education, Upper 28 Pearson Saddle River, Education NJ 7458. All Rights Reserved Summary Half-Adder
More informationEE19D Digital Electronics. Lecture 1: General Introduction
EE19D Digital Electronics Lecture 1: General Introduction 1 What are we going to discuss? Some Definitions Digital and Analog Quantities Binary Digits, Logic Levels and Digital Waveforms Introduction to
More information