Analysis procedure. To obtain the output Boolean functions from a logic diagram, proceed as follows:

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Nicholas Little
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1 Combinational Logic Logic circuits for digital systems may be combinational or sequential. combinational circuit consists of input variables, logic gates, and output variables. 1

2 nalysis procedure To obtain the output Boolean functions from a logic diagram, proceed as follows: 1. Label all gate outputs that are a function of input variables with arbitrary symbols. Determine the Boolean functions for each gate output. 2. Label the gates that are a function of input variables and previously labeled gates with other arbitrary symbols. Find the Boolean functions for these gates. 2

3 nalysis procedure 3. Repeat the process outlined in step 2 until the outputs of the circuit are obtained. 4. By repeated substitution of previously defined functions, obtain the output Boolean functions in terms of input variables. 3

4 OI Logic Implementation This presentation will demonstrate how to Design an OI logic circuit from a Sum-Of- Products (SOP) logic expression. Design an OI logic circuit from a Product-Of- Sums (POS) logic expression. OUT B B C EQULS Logic Expression OI Logic Circuit 4

5 Combinational Logic Circuits n example of an SOP implementation is shown. The SOP expression is an ND-OR combination of the input variables and the appropriate complements. B C D E BC DE X = BC + DE SOP 5

6 Combinational Logic Circuits When the output of a SOP form is inverted, the circuit is called an ND- OR-Invert circuit. The OI configuration lends itself to product-of-sums (POS) implementation. n example of an OI implementation is shown. The output expression can be changed to a POS expression by applying DeMorgan s theorem twice. B BC C X = BC + DE X = BC + DE OI D E DE X = (BC)(DE) DeMorgan X = ( + B + C)(D + E) POS 6

7 Exclusive-OR Logic The truth table for an exclusive-or gate is Notice that the output is HIGH whenever and B disagree. The Boolean expression is X = B + B Inputs Output B X The circuit can be drawn as Symbols: X = 1 B Distinctive shape outline Rectangular 7

8 Exclusive-NOR Logic The truth table for an exclusive-nor gate is Notice that the output is HIGH whenever and B agree. The Boolean expression is X = B + B Inputs Output B X The circuit can be drawn as B X Symbols: = 1 Distinctive shape outline Rectangular 8

9 NND Logic Convert the circuit in the previous example to one that uses only NND gates. Recall from Boolean algebra that double inversion cancels. By adding inverting bubbles to above circuit, it is easily converted to NND gates: C X = C + B B 9

10 Universal Gates NND gates are sometimes called universal gates because they can be used to produce the other basic Boolean functions. Inverter B ND gate B B + B B + B OR gate NOR gate 10

11 NND Logic Recall from DeMorgan s theorem that B = + B. By using equivalent symbols, it is simpler to read the logic of SOP forms. The earlier example shows the idea: C X = C + B B The logic is easy to read if you (mentally) cancel the two connected bubbles on a line. 11

12 NOR Logic lternatively, DeMorgan s theorem can be written as + B = B. By using equivalent symbols, it is simpler to read the logic of POS forms. For example, B C X = ( + B)( + C) gain, the logic is easy to read if you cancel the two connected bubbles on a line. 12

13 Designing OI SOP Logic Circuits Design Steps Implement each Minterm in the logic expression with an ND gate with the same number of inputs as there are variables in the Minterm. (i.e., B = 2 input gate, BC = 3 input gate, BCD = 4 input gate, etc.) OR together the outputs of the ND gates to produce the logic expression. If necessary, gates can be cascaded to create gates with more inputs. 13

14 Example #1: OI Implementation SOP Example Design an OI Logic Circuit for the SOP logic expression shown below. F 2 B CD B CD B 14

15 Example #1: OI Implementation SOP Example Design an OI Logic Circuit for the SOP logic expression shown below. Solution F 2 B CD B CD B 15

16 Example #2: OI Implementation SOP Example Unfortunately, in this class, we only have access to (2) input OR gates and (2) & (3) input ND gates. Limiting your design to these gates, redesign the OI Logic Circuit for the SOP expression in the previous example. 16

17 Example #2: OI Implementation SOP Example Unfortunately, only (2) input OR gates and (2) & (3) ND gates exist in hardware. Limiting your design to these gates, redesign the OI Logic Circuit for the SOP expression in the previous example. Solution 17

18 Designing OI POS Logic Circuits Design Steps Implement each Maxterm in the logic expression with an OR gate with the same number of inputs as there are variables in the Maxterm. (i.e., +B = 2 input gate, +B+C = 3 input gate, +B+C+D = 4 input gate, etc.) ND together the outputs of the OR gates to produce the logic expression. If necessary, gates can be cascaded to create gates with more inputs. 18

19 Example #3: OI Implementation POS Example Design an OI Logic Circuit for the POS logic expression shown below. F 4 W X Y Z W X Y W Z 19

20 Example #3: OI Implementation POS Example Design an OI Logic Circuit for the POS logic expression shown below. Solution F 4 W X Y Z W X Y W Z 20

21 Example #4: OI Implementation POS Example Limiting your design to only (2) input OR gates and (2) & (3) input ND gates, redesign the OI Logic Circuit for the POS logic expression in the previous example. 21

22 Example #4: OI Implementation POS Example Limiting your design to only (2) input OR gates and (2) & (3) input ND gates, redesign the OI Logic Circuit for the POS logic expression in the previous example. Solution 22

23 Example F 2 = B + C + BC; T 1 = + B + C; T 2 = BC; T 3 = F 2 T 1 ; F 1 = T 3 + T 2 F 1 = T 3 + T 2 = F 2 T 1 + BC = BC + B C + B C + BC 23

24 Derive truth table from logic diagram We can derive the truth table in Table 4-1 by using the circuit of Fig

Digital Fundamentals

Digital Fundamentals Tenth Edition Floyd hapter 5 Floyd, Digital Fundamentals, th ed 28 Pearson Education 29 Pearson Education, Upper Saddle River, NJ 7458. ll Rights Reserved ombinational Logic ircuits