Chapter 2 Introduction to Logic Circuits

Transcription

1 Chapter 2 Introduction to Logic Circuits Logic unctions and circuits Boolean algebra Snthesis o digital circuits Introduction to CAD tools Introduction to VHDL Logic unctions and Circuits and 2 are binar variables, that ma take on onl one o two Possible values, i.e., or Figure 2.6. A truth table or the AND and OR operations. Chapter 2-2

2 n n (a) AND gates n n (b) OR gates (c) NOT gate Figure 2.8. The basic gates. Chapter A B (, ) 2 2 A B (a) Network that implements = + 2 (b) Truth table 2 A B (c) Timing diagram Time 2 g (d) Network that implements g = + 2 Figure 2.. An eample o logic networks. Chapter 2-4

3 Boolean Algebra Aioms o Boolean Algebra A) = A ) + = A2) = A2 ) + = A3) = = A3 ) + = + = A4) i =, then = A4 ) i =, then = Chapter 2-5 Boolean Algebra Single variable theorems T) = T ) + = T2) = T2 ) + = T3) = T3 ) + = T4) = T4 ) + = T5) = Chapter 2-6

4 Boolean Algebra Two and three variable theorems T6) = T6 ) + = + T7) ( ) = ( ) T7 ) + ( + ) = ( + ) + T8) ( + ) = + T8 ) + = ( + ) ( + ) T9) + = T9 ) ( + ) = T) + = T ) ( + ) ( + ) = T) ( ) = + T ) ( + ) = T2) + = + T2 ) ( + ) = T3) + + = + T3 ) ( + ) ( + ) ( + ) = ( + ) ( + ) Precedence rule: in the absence o parentheses, operations in logic epressions must be perormed in the order: NOT, AND, and then OR Chapter 2-7 Boolean Algebra Principle o dualit: given a logic epression its dual is obtained b replacing all + operators with operators, and vice versa, and b replacing all s with s, and vice versa. The dual o an true statement (aiom or theorem) in Boolean algebra is also true. T6 & T6 are called Commutative propert T7 & T7 are called Associative propert T8 & T8 are called Distributive propert T9 & T9 are called Absorption propert T & T are called Combining propert T & T are called DeMorgan s theorem T3 & T3 are called Consensus theorem Chapter 2-8

5 Boolean Algebra Eample: Appl theorems o Boolean Algebra to prove that the let and right hand sides o the ollowing logic equation are identical = Chapter 2-9 Boolean Algebra The Venn Diagram Graphical illustration o various operations and relations in the algebra o sets A set s is a collection o elements that are said to be members o s In Venn diagram the elements o a set are represented b the area enclosed b a square, circle or ellipse In Boolean algebra there are onl two elements in the universe, i.e. {,}. Then the area within a contour corresponding to a set s denotes that s =, while the area outside the contour denotes s = In a Venn diagram we shade the area where s = Chapter 2-

6 Boolean Algebra (a) Constant (b) Constant (a) (d) (c) Variable (d) (b) + (e) (e) (g) () (h) + + Figure 2.2. The Venn diagram representation. (c) ( + ) () + Figure 2.3. Veriication o the distributive propert Chapter 2- ( + ) = Figure 2.4. Veriication o + + = + Chapter 2-2

7 Snthesis o digital circuits Snthesis is the process o generating a circuit that realies a unctional behavior o a logic sstem rom a given description (stated in orm o verbal statements, truth table, K-map, state diagram, etc.) Eample: Snthesie a logic unction that realies the ollowing truth table. Use AND, OR, and NOT gates Figure 2.5. A unction to be snthesied. Chapter 2-3 Snthesis o digital circuits 2 (a) Canonical sum-o-products 2 (b) Minimal-cost realiation Figure 2.6. Two implementations o a unction in Figure 2.5. Chapter 2-4

8 Snthesis o digital circuits Terminologies: Literal: a variable or the complement o a variable Product term: a single literal or logical product (AND) o two or more literals n-variable minterm: a product term with n literals. It assumes a value o or eactl one row o a unction s truth table (i.e. input combination) Sum-o-products (SOP): logical sum (OR) o product (AND) terms Canonical SOP: An SOP where each product term is a minterm. Sum term: a single literal or a logical sum o two or more literals. n-variable materm: a sum term with n literals. It assumes a value o or eactl one row o a unction s truth table (i.e. input combination) Product-o-sums (POS): is logical product o sum terms Canonical POS: A POS where each sum term is a materm Chapter 2-5 Snthesis o digital circuits Figure 2.7 Three-variable minterms and materms. Chapter 2-6

9 Snthesis o digital circuits Eample: For the three variable unction given b the ollowing truth table, determine the minterms, materms, canonical SOP, canonical POS, minterm list or on-set, materm list or o-set, minimal SOP and minimal POS b algebraic manipulations. Figure 2.8. A three-variable unction. Chapter 2-7 Snthesis o digital circuits 2 3 (a) A minimal sum-o-products realiation 3 2 (b) A minimal product-o-sums realiation Figure 2.9. Two realiations o the unction in Figure 2.8. Chapter 2-8

10 Snthesis o digital circuits NAND and NOR gates and their DeMorgan equivalent representations n n (a) NAND gates n n (b) NOR gates Chapter 2-9 Snthesis o digital circuits (a) 2 = (b) + 2 = 2 Figure 2.2. DeMorgan s equivalents o NAND and NOR gates. Chapter 2-2

11 Snthesis o digital circuits Converting a AND-OR realiation o an SOP to a NAND-NAND realiation Converting a OR-AND realiation o a POS to a NOR-NOR realiation Chapter 2-2 Snthesis o digital circuits Eample: Snthesie a logic circuit rom a verbal description o a problem or a three-wa light control (section 2.8., pg. 52) 2 3 (a) Sum-o-products realiation 3 2 Eercise: Convert the SOP and POS circuit realiations to NAND-NAND and NOR-NOR circuits, respectivel. (b) Product-o-sums realiation Chapter 2-22

12 Introduction to CAD tools Computer Aided Design (CAD) tools automate the processes o: Design Snthesis Optimiation Simulation: Functional Timing Phsical implementation o logic circuits on target devices Quartus II rom Altera Corporation is such sotware used in this course. Chapter 2-23 Introduction to CAD tools Design entr: description o what the desired circuit is supposed to do and the ormation o its general structure. This step o a design requires design eperience & intuition so it is done b a designer. Schematic Capture graphical entr Hardware Description Language (eg. VHDL, Verilog, ABEL) Computer program describing how a hardware should behave VHDL & Verilog are industr standards and thus portable to dierent target hardware and CAD tools Designer can ocus on the unctionalit o the desired circuit without being overl concerned about the implementation technolog Both Schematic & HDL design entr methods allow modular and hierarchical designs to manage sstem compleit Chapter 2-24

13 Introduction to CAD tools Snthesis process o generating a logic circuit rom an initial speciication given in schematic diagram or HDL. It involves compiling or translating the design entr (eg. VHDL) into a set o logic epressions that describe the logic unctions Oten the snthesis process is ollowed b optimiation or speciied goals: HW cost or time dela Functional Simulation used to veri that the design will unction as epected Assumes that the logic equations generated during snthesis will be implemented with perect gates with no propagation delas Test sequences are applied or which the simulator generates outputs Chapter 2-25 Introduction to CAD tools Phsical Design the tool determines eactl how to implement the circuit on a given chip Maps a circuit speciied in logic epressions into a realiation that makes use o the resources available on the target chip Determines the placement o speciic logic elements & their interconnection Timing Simulation a simulation that takes into account the actual delas o signals as the are processed b the logic elements and propagate through the wires Helps determine i the generated circuit satisies the timing requirements o the speciication Chip Coniguration or programming this step involves the implementation o the circuit on an actual target chip Chapter 2-26

14 Design conception DESIGN ENTRY Schematic capture VHDL Snthesis Functional simulation No Design correct? Yes Phsical design Timing simulation No Timing requirements met? Chip coniguration Figure A tpical CAD sstem. Chapter 2-27 Introduction to VHDL VHDL = Ver High Speed Integrated Circuit (VSHIC) Hardware Description Language, an IEEE standard language Original standard was adopted in 987 and called IEEE 76. Revised standard adopted in 993 and called IEEE 64. It was subsequentl updated in 2 and 22. Initiall intended as a documentation language or describing the structure o comple circuits, and or modeling the behavior o digital circuits or simulation. It has now become a popular tool or design entr in CAD sstems, which snthesie the VHDL code into hardware implementation. VHDL is a sophisticated language so onl a subset o eatures or use in snthesis will be covered in this course. The required eatures will be introduced when needed. Chapter 2-28

15 Introduction to VHDL Digital signals in VHDL are represented b a data object o tpe BIT. BIT objects can have onl one o two possible values: or. A VHDL construct called entit is used to declare the input and output interaces o a circuit or module. The entit must be assigned a name. The input and output signals or an entit are called its ports, and the are identiied b the keword PORT. Each port has an associated mode that speciies whether it is input (IN) to the entit or output (OUT) rom the entit. Each port is a signal hence has an associated tpe. Chapter 2-29 Introduction to VHDL 2 3 Figure 2.3. A simple logic unction. ENTITY eample IS PORT (, 2, 3 : IN BIT ; : OUT BIT ) ; END eample ; Figure 2.3. VHDL entit declaration or the circuit in Figure 2.3. Chapter 2-3

16 Introduction to VHDL An entit speciies the input and output signals or a circuit, but no inormation about its internal unctions. The circuit s unctionalit must be speciied with a VHDL construct called architecture. An architecture must be given a name and attached to a corresponding entit. VHDL provides built-in Boolean operators (AND, OR, NOT, NAND, NOR, XOR, and XNOR) that could be used or describing the logical unctions o an architecture VHDL signal assignment operator <= could be used to assign the result o a logic epression on the right-hand side o the operator to an output signal on the let. Chapter 2-3 Introduction to VHDL Figure Complete VHDL code or the circuit in Figure 2.3. As a simple analog, an entit is equivalent to a smbol in a schematic Diagram and the architecture speciies the logic circuitr Chapter 2-32

17 Introduction to VHDL Chapter 2-33