Digital Circuits II Lecture 6. Lab Demonstration 3 Using Altera Quartus II to Determine Simplified Equations & Entering Truth Table into VHDL

Transcription

1 Digital Circuits II Lecture 6 Lab Demonstration 3 Using Altera Quartus II to Determine Simplified Equations & Entering Truth Table into VHDL References (Text Book): 1) Digital Electronics, 9 th editon, by William Kleitz, published by Pearson Spring 2015 Paul I-Hai Lin, Professor Dept. of Computer, Electrical and Information Technology Indiana University-Purdue University Fort Wayne Prof. Paul Lin 1 Lab Demo 3 Extra Features of Altera Quartus II Analysis & Synthesis Messages (no used input) Simplification Equations through Altera Quartus II Processing > Compilation Report Tools > Netlist Viewer Block Symbol file (*.bdf) creation Using VHDL features to enter truth table: SIGNAL, vector (bit array) WITH, SELECT, WHEN Prof. Paul Lin 2 1

2 VHDL Code for Example 5-9 The Boolean Equation X = A + B B + C B --ex5_9.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ex5_9 IS PORT( a,b,c : IN std_logic; x : OUT std_logic); END ex5_9; ARCHITECTURE arc OF ex5_9 IS BEGIN x <=((a OR NOT b) AND (b OR c))and b; END arc; Prof. Paul Lin 3 Altera Quartus II Simplified Equation and Form of the Circuit Before Synthesize the Circuit Create New Project Assignments > Devices (EP3C16F484C6) File > New File > VHDL file (save as ex5_9.vhd) Assignments > Settings > Simulator Settings (Functional) Processing > Start Compilation Processing > Compilation Report ( to see Analysis & Synthesis Messages) Warning: Design contains 1 input pin(s) that do not drive logic No output dependent on input pin (a) Node Finder > List (to show a, b, c, and x) Create ex5_9.vwf file Processing > Generate Functional Simulation Netlist Processing > Start Simulation Prof. Paul Lin 4 2

3 Altera Quartus II Simplified Equation and Form of the Circuit Before Synthesize the Circuit Simulation Result X is HIGH for a AND b, regardless of c Prof. Paul Lin 5 Altera Quartus II Simplified Equation and Form of the Circuit Before Synthesize the Circuit Create Block Symbol file File > New > Other Files > Block Symbol File Ex5_9.bdf Connect inputs: a, b, c; and output x ex5_9 a b c x inst Prof. Paul Lin 6 3

4 Altera Quartus II Simplified Equation and Form of the Circuit Before Synthesize the Circuit View Simplified Equation Tools > Chip Planner > Edit > find > Find What: x > Find Next > Cancel In the Fan-In column click [< GoTo] See the equation listed: A Prof. Paul Lin 7 Altera Quartus II Simplified Equation and Form of the Circuit Before Synthesize the Circuit Quartus II Operators: & AND operator,! NOT Operator, # OR Operator, $ EX-OR operator Tools > Netlist Viewers > technology Map Viewer Post Mapping Prof. Paul Lin 8 4

5 VHDL Code with Simplified Equation Click on Hide Content/Display Content to see Gates Prof. Paul Lin 9 VHDL Code with Simplified Equation The Boolean Equation X = A + B B + C B The simplified equation Y = AB --ex5_9.vhd LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ex5_9 IS PORT( a,b,c : IN std_logic; x, y : OUT std_logic); END ex5_9; ARCHITECTURE arc OF ex5_9 IS BEGIN x <=((a OR NOT b) AND (b OR c))and b; y <= a AND b; -- added to show the result after the simplification END arc; Prof. Paul Lin 10 5

6 VHDL Code with Simplified Equation The Boolean Equation X = A + B B + C B The simplified equation Y = AB Observed identical outputs at x and y Prof. Paul Lin 11 Simplified Boolean Equation using Altera Quartus II - Example 5-17 Example 5-17 (pages ): simplify the two equations X = ((AB + (B + C)) and Y = (AB) + (B+C) --ex5_17.vhd LIBRARY ieee; --Using VHDL to Simplify Equations USE ieee.std_logic_1164.all; ENTITY ex5_17 IS PORT( a,b,c : IN std_logic; x, y : OUT std_logic); END ex5_17; ARCHITECTURE arc OF ex5_17 IS BEGIN x<=not((a AND b) OR (NOT b OR c)); y<=(a NAND b) OR (b NOR c); END arc; Prof. Paul Lin 12 6

7 Simplified Boolean Equation using Altera Quartus II - Example 5-17 Tools > Netlist Viewers > technology Map Viewer Post Mapping Prof. Paul Lin 13 Simplified Boolean Equation using Altera Quartus II - Example 5-17 Tools > Netlist Viewers > technology Map Viewer Post Mapping Click on Hide Content/Display Content to see Gates Write the equations from Netlist Viewer X = ((AB + (B + C)) = A BC Y = (AB) + (B+C) = A + B = (AB) Prof. Paul Lin 14 7

8 Entering a Truth Table in VHDL using a Vector Signal - Example 5-22 Example 5-22 (page 194): Design a logic circuit that can be used to tell when a 3-bit binary number is within the range of 2 (010) to 6 (110). Also test the logic using the DE0 board. Prof. Paul Lin 15 Entering a Truth Table in VHDL using a Vector Signal - Example 5-22 LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ex5_22 IS PORT( a,b,c : IN std_logic; x : OUT std_logic); END ex5_22; ARCHITECTURE arc OF ex5_22 IS SIGNAL input : std_logic_vector(2 DOWNTO 0); BEGIN input(2)<=a; --move a to element 2 of the internal vector signal input(1)<=b; --move b to element 1 of the internal vector signal input(0)<=c; --move c to element 0 of the internal vector signal. Prof. Paul Lin 16 8

9 Entering a Truth Table in VHDL using a Vector Signal - Example 5-22 ARCHITECTURE arc OF ex5_22 IS SIGNAL input : std_logic_vector(2 DOWNTO 0); BEGIN input(2)<=a; --move a to element 2 of the internal vector signal input(1)<=b; --move b to element 1 of the internal vector signal input(0)<=c; --move c to element 0 of the internal vector signal WITH input SELECT x <= '0' WHEN "000", -- x equals 0 when input equals "000" '0' WHEN "001", -- x equals 0 when input equals "001" '1' WHEN "010", -- x equals 1 when input equals "010" '1' WHEN "011", -- x equals 1 when input equals "011" '1' WHEN "100", -- x equals 1 when input equals "100" '1' WHEN "101", -- x equals 1 when input equals "101" '1' WHEN "110", -- x equals 1 when input equals "110" '0' WHEN "111", -- x equals 0 when input equals "111" '0' WHEN others; END arc; Prof. Paul Lin 17 Entering a Truth Table in VHDL using a Vector Signal - Example 5-22 Simulation Output X is HIGH for 2, 3, 4, 5, and 6 Prof. Paul Lin 18 9

10 Entering a Truth Table in VHDL using a Vector Signal - Example 5-22 Tools > Netlist Viewers > technology Map Viewer Post Mapping Prof. Paul Lin 19 Overflow sensing for a Water reclamation plant Example 5-23 Example 5-23 (page 195): A water reclamation plans needs to have warning system to monitor the three water overflow holding tanks. Each tank has a HIGH/LOW level sensor. Design a system that activates a warming alarm whenever two or more tanks levels are HIGH. Also test the logic using the DE0 board. Prof. Paul Lin 20 10

11 Overflow sensing for a Water reclamation plant Example ex5_23.vhd -- Chemical Tank Monitoring -- Alarm is high for any combination of two or more tanks high LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY ex5_23 IS PORT( tank : IN std_logic_vector(2 downto 0); alarm : OUT std_logic); END ex5_23; Prof. Paul Lin 21 Overflow sensing for a Water reclamation plant Example 5-23 ARCHITECTURE arc OF ex5_23 IS BEGIN WITH tank SELECT alarm <= '0' WHEN "000", '0' WHEN "001", '0' WHEN "010", '1' WHEN "011", '0' WHEN "100", '1' WHEN "101", '1' WHEN "110", '1' WHEN "111", '0' WHEN others; END arc; Prof. Paul Lin 22 11

12 Overflow sensing for a Water reclamation plant Example 5-23 Prof. Paul Lin 23 Reference: DEO Board I/Os Prof. Paul Lin 24 12

13 Reference: DEO Board I/Os Prof. Paul Lin 25 Summary & Conclusion Prof. Paul Lin 26 13