CENG3430 RAPID PROTOTYPING OF DIGITAL SYSTEMS

Transcription

1 VHDL 0 (v.7a) : Introduction 1 CENG3430 RAPID PROTOTYPING OF DIGITAL SYSTEMS YANG Ming-Chang mcyang@cse Room 906 SHB WONG Kin Hong khwong@cse Room 907 SHB

2 VHDL 0 (v.7a) : Introduction 2 CENG3430 Rapid Prototyping of Digital Systems You will learn: The hardware description language E.g., VHDL or Verilog Techniques to build a logic system E.g. Building blocks of a Central Processing Unit (CPU) High speed logic circuits analysis: time delay estimation, testing, power supply stability, etc. Ex: VHDL AND-gate Program 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch Write VHDL code, then it will generate the hardware chip automatically

3 VHDL 0 (v.8) : Introduction 3 CENG3430 Rapid Prototyping of Digital Systems Course Professors: YANG Ming-Chang (mcyang@cse.cuhk.edu.hk) WONG Kin Hong (khwong@cse.cuhk.edu.hk) Course Tutors: Zheng Zhiliang (zlzeng@cse.cuhk.edu.hk) Lo Sheung lai, Lester(sllo@cse.cuhk.edu.hk) Course Time: Lecture: Mon. 4:30-6:15pm (Venue: ERB 404) Laboratory and Tutorial: Tue. 5:30-7:15pm (Venue: SHB-102) Course Website:

4 VHDL 0 (v.8) : Introduction 4 CENG3430 Rapid Prototyping of Digital Systems Weeks Date Lecture Lab Week 1 Jan. 8~9 VHDL 0 & VHDL 1: Introduction No Lab Week 2 Jan. 15~16 VHDL 2: Identifiers, Data Objects and Types Lecture Week 3 Jan. 22~23 VHDL 3: Basic Operators and Arch. Body Introduce Vivado + Software Simulation Week 4 Jan. 29~30 VHDL 4: Building Blocks of a Computer Implement OR Gate Week 5 Feb. 5~6 VHDL 5: Finite State Machines Tri-state Logic + Simulation Week 6 Feb. 12~13 VHDL 6: FSM Examples 4-to-1 Multiplexer Week 7 Feb. 19~20 New Years New Years Week 8 Feb. 26~27 VHDL 7: Use of Signals Serial-in-parallel-out Shift Register Week 9 Mar. 5~6 VHDL 8: Application Examples Driving the Seven Segment Display Week 10 Mar. 12~13 VHDL 9: Programmable Logic Families Software Stopwatch Week 11 Mar. 19~20 New Applications on FPGAs Linux GPIO + LED Week 12 Mar. 26~27 Free Project Project Consultations Week 13 Apr. 2~3 Reading Week Reading Week Week 14 Apr. 9~10 HS_i: Power Supply Systems Project Demo Week 15 Apr. 16~17 HS_ii: Transmission Lines Project Demo

5 VHDL 0 (v.8) : Introduction 5 CENG3430 Rapid Prototyping of Digital Systems Marking Scheme and Exams: Part 1 (50%): Class exercises, laboratory exercises, quizzes and project assignments are accounted for 50% of the overall assessment. Part 2 (50%): The final exam is 50% of the overall assessment. Note: Please check your marks regularly; the marks will not be changed 2 weeks after published online.

6 VHDL 0 (v.7a) : Introduction 6 A QUICK RUN THROUGH Overview

7 VHDL 0 (v.7a) : Introduction 7 Overview What is VHDL used for? To design Hardware systems (an industrial standard) Microprocessors: Arm7 etc. New digital systems: e.g. mobile phone, camera chips

8 VHDL 0 (v.7a) : Introduction 8 Motivations Learn to design digital systems. Provide knowledge for you to : Design products: Robots controllers, media players, portable games, mobile phones. Advanced examples: Image processing Computer vision Super computer Start a business.

9 VHDL 0 (v.7a) : Introduction 9 Examples of Digital System Designs Mass products Media players Mobile phones Novel products Wearable devices Robots Research Real time edge detection for computer vision FPGA-based deep learning acceleration

10 VHDL 0 (v.7a) : Introduction 10 To learn Design digital processing components using programmable logic. Two existing Methods: (a) Schematic Too complicated but is suitable to describe the top level design like a data flow block diagram. (b) Language (e.g. VHDL--Very- High-Speed-Integrated-Circuits Hardware Description Language) Each module in the schematic can be written in VHDL. 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch

11 VHDL 0 (v.7a) : Introduction 11 DIGITAL DESIGN Work Flow

12 VHDL 0 (v.7a) : Introduction 12 Digital Design Work Flow Idea generation Drafting on paper Design the chip (use VHDL) Test 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch Manufacturing production line design Quality control

13 VHDL 0 (v.7a) : Introduction 13 WE USE IN OUR LAB Hardware: FPGA (Field Programmable Gate Array) The hardware can be reprogrammable, so you can change your design rapidly and easily with no additional hardware manufacturing cost. Software: VHDL (Very-High-Speed-Integrated- Circuits Hardware Description Language)

14 VHDL 0 (v.7a) : Introduction 14 Re-programmable Hardware: FPGA Field Programmable Gate Array What is inside an FPGA? 1) IOB: Input/Output Block Input/output of FPGA 2) CLB: Configurable Logic Block (static ram based) Change the CLBs to get the desired functions 3) Programmable Interconnects Interconnect IOBs and CLBs From

15 VHDL 0 (v.8) : Introduction 15 Inside a CLB (Configurable Logic block ) The CLB is a fixed design but you can change the logic function by reprogramming the bits in the logic function lookup table. This will change the overall logic function of the CLB. CLB FPGA CLB (Configurable Logic block )

16 VHDL 0 (v.7a) : Introduction 17 Software: To program an FPGA Use a schematic: (Top level design to merge modules) or/and Use a language VHDL (for each module) 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch

17 VHDL 0 (v.8) : Introduction 18 Development cycle Schematic (diagram) VHDL Language 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <=a and b; 7 end and2_arch Simulation

18 VHDL 0 (v.8) : Introduction 19 An example: AND gate in VHDL 1 entity and2 is port (a,b : in std_logic; 2 c : out std_logic); 3 end and2 4 architecture and2_arch of and2 5 begin 6 c <= a and b; 7 end and2_arch a b c <= a and b The chip c

19 VHDL 0 (v.7a) : Introduction 20 Test bench and timing simulation use simulation to see if your design is correct or not. See the tutorial at NG3430_1617_Tutorial_1_7a_test_bench.pptx You create some input patterns and see if the outputs are behaving correctly or not outputs Inputs

20 VHDL 0 (v.7a) : Introduction 21 Summary of VHDL For hardware Design Parallel language (not sequential) Different! (not the same as C++ or Java) VHDL is the industrial standard for CE.

21 VHDL 0 (v.7a) : Introduction 22 COMPUTER ENGINEERING MARKET

22 VHDL 0 (v.7a) : Introduction 23 TSMC (Taiwan Semicon. Manufacturing Comp.) 台灣積體電路製造股份有限公司 From Wiki: Has the largest asset in Taiwan stock market, One of the World's largest dedicated 华为技术有限公司 independent semiconductor foundry. Products: Apple iphone6 plus A8-cpu Relation to VHDL Design idea Write VHDL TSMC Chips

23 VHDL 0 (v.7a) : Introduction 24 Huawei Technologies Co. Ltd 华为技术有限公司 From Wiki: Telecom equipment manufacture China large private company 华为技术有限公司 ( ) Products: the second-largest supplier of mobile telecommunications infrastructure equipment in the world (after Ericsson).

24 VHDL 0 (v.7a) : Introduction 25 References See course web page Digital Systems Design Using VHDL, Charles H. Roth (first or second edition) Rapid Prototyping of Digital Systems, by Hamblen, James etal. Springer (read_online) Digital Design: Principles and Practices, 4/E John F. Wakerly, Prentice Hall. High-Speed Digital Design: A Handbook of Black Magic by Howard W. Johnson and Martin Graham Prentice Hall. BOOKBOON (Free text books)

25 VHDL 0 (v.7a) : Introduction 29 TRI-STATE LOGIC The concept of tri-state logic is essential in computer design, so we want to revise these techniques before we move on.

26 VHDL 0 (v.7a) : Introduction 30 Appendix: Tri-state logic **At the float state, the wire is cut Input OE (input) Output 0 0 Z(Float) 1 0 Z(Float) Input Output Enable (OE) Output

27 Tri-state equivalent circuit VHDL 0 (v.7a) : Introduction 31 (using output connect/cut view) Input Output Output Enable (OE) Same as Input Output Enable (OE) Output OE=1, switch close OE=0, switch open

28 VHDL 0 (v.7a) : Introduction 32 Alternatively: We can treat the Tri-state equivalent circuit using the Rout impedance view A tri-state circuit diagram Input Output Enable (OE) Output Tri-state equivalent circuit : Rout impedance view to explain the concept of tri-stat OE (output enable) controls the value of Rout Input Same as Rout Output Output Enable (OE) When OE=1, Rout = small, (e.g. 50 Ω ) When OE=0, Rout = infinity (e.g. 10 MΩ)

29 VHDL 0 (v.7a) : Introduction 33 Student ID:,Date: Name: Exercise 0.1:Tri-state logic with pull up resistor Output-Enable Input OE (input) Output 0 0? 1 0? 0 1? 1 1? Input Output Enable (OE) 10K 5V Output **At float the wire is cut A pull-up resistor is a resistor used to ensure a known state for a signal

30 VHDL 0 (v.7a) : Introduction 34 Exercise 0.2: Use Rout (Impedance view) to explain the result of exercise 0.1 Input1 Output- Enable OE (input) Output Equivalent Rout (10M or 50 ) 0 0? _1?? 1 0? _1?? 0 1? _0?? 1 1? _1?? Draw equivalent circuit and find output Voltage Resistance view Ohm s Law Hirchhoff Circuit Law:

31 VHDL 0 (v.7a) : Introduction 35 Exercise 0.3 Application 1 of Tri-state logic: Input/Output pin OE1 controls the traffic. Fill in the cells with?. A Directional control(oe1) B A Output Enable OE1 (input) 0 0? 1 0?? 1 0 B? 1 1

32 Exercise 0.4 Application 2 of Tri-state logic: Transceivers for I/O data pins When T =1, A->B; T controls the traffic, when /OE=1, IO pins A,B are disabled Fill in the cells with?. VHDL 0 (v.7a) : Introduction 36 T A Output Enable /OE1 (input) 1 0 0?? B Which controls which A 0 1 0?? T B?? 1 Float? /OE? Float 1??

33 VHDL 0 (v.7a) : Introduction 37 All data-lines are transceiver buffers A good controller will enable the CPU to read/write RAM, and read ROM RAM data lines /OE1, T1 transceivers CPU data lines transceivers /OE3, T3 /OE2, T2 transceivers ROM data lines

34 Exercise 0.5 : List OE1,2,3 and T1,2,3 for the followings cases a) CPU writes to RAM: /OE1=, /OE2, /OE3=, T1, T2=, T3 b) CPU reads from ROM /OE1=, /OE2, /OE3=, T1, T2=, T3 c) CPU reads from RAM VHDL 0 (v.7a) : Introduction 38 /OE1=, /OE2, /OE3=, T1, T2=, T3 RAM data lines /OE1, T1 A transceivers CPU data lines A transceivers B B /OE3, T3 /OE2, T2 transceivers B A ROM data lines

35 Exercise 0.6 Application 3 of Tri-state logic: Selection of control signal (resolved logic) Output depends on Input_A if OE is _? Output depends on Input_B if OE is _? Discuss the operation of this circuit. 39 Input_A Output Input_B OE VHDL 0 (v.7a) : Introduction

36 VHDL 0 (v.7a) : Introduction 40 Exercise 0.7 Fill in?. Is it a nor-gate or an or-gate? Discuss the operation of this circuit. Answer : Pull-up Resistor OE1 OE2 Output 5V 0 0? 10K 1 0? Output 0V 0 1? OE1 1 1? OE2 0V