Welcome to 6.S084! Computation Structures (special)
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1 Welcome to 6.S084! Computation Structures (special) Spring 2018
2 6.S084 Course Staff Instructors Arvind Daniel Sanchez Teaching Assistants Silvina Hanono Wachman Thomas Bourgeat Kathy Camenzind Josh Noel Brian Wheatman Andy Wright Guowei Zhang February 6, 2018 L01-2
3 Computing Devices Then ENIAC, tons, 200KW, ~1000 ops/sec February 6, 2018 L01-3
4 Computing Devices Now Typical 2018 laptop 1kg, 10W, 10 billion ops/s February 6, 2018 L01-4
5 Computing Devices Now Typical 2018 laptop 1kg, 10W, 10 billion ops/s February 6, 2018 L01-4
6 An Introduction to the Digital World Application software Operating systems Virtual memory Interpretation & compilation Data and control structures Programmable architectures Combinational & sequential logic Devices Materials Atoms Virtual machines Programming languages Instruction set + memory Bits, Logic gates February 6, 2018 L01-5
7 An Introduction to the Digital World Application software Operating systems Virtual memory Interpretation & compilation Data and control structures Programmable architectures Combinational & sequential logic Devices Materials Atoms Virtual machines Programming languages Instruction set + memory Bits, Logic gates February 6, 2018 L01-5
8 The Power of Engineering Abstractions Good abstractions let us reason about behavior while shielding us from the details of the implementation. Virtual machines Programming languages Instruction set + memory Bits, Logic gates February 6, 2018 L01-6
9 The Power of Engineering Abstractions Good abstractions let us reason about behavior while shielding us from the details of the implementation. Corollary: implementation technologies can evolve while preserving the engineering investment at higher levels. Virtual machines Programming languages Instruction set + memory Bits, Logic gates February 6, 2018 L01-6
10 The Power of Engineering Abstractions Good abstractions let us reason about behavior while shielding us from the details of the implementation. Corollary: implementation technologies can evolve while preserving the engineering investment at higher levels. Leads to hierarchical design: Limited complexity at each level shorten design time, easier to verify Reusable building blocks Virtual machines Programming languages Instruction set + memory Bits, Logic gates February 6, 2018 L01-6
11 Our Focus: Programmable General-Purpose Processors February 6, 2018 L01-7
12 Our Focus: Programmable General-Purpose Processors Microprocessors are the basic building block of computer systems Understanding them is crucial even if you do not plan to work as a hardware designer February 6, 2018 L01-7
13 Our Focus: Programmable General-Purpose Processors Microprocessors are the basic building block of computer systems Understanding them is crucial even if you do not plan to work as a hardware designer Microprocessors are the most sophisticated digital systems that exist today Understanding them will help you design all kinds of hardware February 6, 2018 L01-7
14 Our Focus: Programmable General-Purpose Processors Microprocessors are the basic building block of computer systems Understanding them is crucial even if you do not plan to work as a hardware designer Microprocessors are the most sophisticated digital systems that exist today Understanding them will help you design all kinds of hardware We will use a new methodology that emphasizes learning-by-doing Building systems is the best way to understand them February 6, 2018 L01-7
15 Our Focus: Programmable General-Purpose Processors Microprocessors are the basic building block of computer systems Understanding them is crucial even if you do not plan to work as a hardware designer Microprocessors are the most sophisticated digital systems that exist today Understanding them will help you design all kinds of hardware We will use a new methodology that emphasizes learning-by-doing Building systems is the best way to understand them By the end of the term you would have designed a small multicore from scratch! February 6, 2018 L01-7
16 We Rely on Modern Design Tools Bluespec SystemVerilog Design Flow BSV source Bluespec Compiler Verilog RTL Bluespec Simulator Cycle Accurate Vivado Simulator Vivado Synthesis Design Compiler VCD output Power Analysis Designs are always expressed in a highlevel textual notation, i.e., programming language, which is compiled to generate circuit descriptions Gates ASIC February 6, 2018 L01-8
17 We Rely on Modern Design Tools Bluespec SystemVerilog Design Flow BSV source Bluespec Compiler Verilog RTL Bluespec Simulator Cycle Accurate Vivado Simulator Vivado Synthesis Design Compiler VCD output Power Analysis Designs are always expressed in a highlevel textual notation, i.e., programming language, which is compiled to generate circuit descriptions Gates ASIC February 6, 2018 L01-8
18 We Rely on Modern Design Tools Bluespec SystemVerilog Design Flow BSV source Bluespec Compiler Verilog RTL Bluespec Simulator Cycle Accurate Vivado Simulator Vivado Synthesis Design Compiler VCD output Power Analysis Designs are always expressed in a highlevel textual notation, i.e., programming language, which is compiled to generate circuit descriptions Gates ASIC February 6, 2018 L01-8
19 Key Differences with Learning-by-doing methodology using modern tools Modern tools let us go further Labs cover everything we teach Software-based methodology helps develop programming skills February 6, 2018 L01-9
20 Key Differences with Learning-by-doing methodology using modern tools Modern tools let us go further Labs cover everything we teach Software-based methodology helps develop programming skills More emphasis on labs and project than on quizzes February 6, 2018 L01-9
21 Key Differences with Learning-by-doing methodology using modern tools Modern tools let us go further Labs cover everything we teach Software-based methodology helps develop programming skills More emphasis on labs and project than on quizzes More focus on processor organization February 6, 2018 L01-9
22 Key Differences with Learning-by-doing methodology using modern tools Modern tools let us go further Labs cover everything we teach Software-based methodology helps develop programming skills More emphasis on labs and project than on quizzes More focus on processor organization Will not cover low-level (analog) circuit design February 6, 2018 L01-9
23 Key Differences with Learning-by-doing methodology using modern tools Modern tools let us go further Labs cover everything we teach Software-based methodology helps develop programming skills More emphasis on labs and project than on quizzes More focus on processor organization Will not cover low-level (analog) circuit design We assume you already have basic programming skills, at the level of or equivalent Contact us if you are not sure you meet this February 6, 2018 L01-9
24 Course Mechanics Three modules: Digital design: Combinational and sequential circuits (L1-7) Computer organization: Instruction sets, simple processor design, caches, virtual memory, and operating systems (L8-14) High-performance processors: pipelining and parallelism (L15-24) February 6, 2018 L01-10
25 Course Mechanics Three modules: Digital design: Combinational and sequential circuits (L1-7) Computer organization: Instruction sets, simple processor design, caches, virtual memory, and operating systems (L8-14) High-performance processors: pipelining and parallelism (L15-24) 2 lectures/week (Arvind + Daniel): handouts on website February 6, 2018 L01-10
26 Course Mechanics Three modules: Digital design: Combinational and sequential circuits (L1-7) Computer organization: Instruction sets, simple processor design, caches, virtual memory, and operating systems (L8-14) High-performance processors: pipelining and parallelism (L15-24) 2 lectures/week (Arvind + Daniel): handouts on website 2 recitations/week (Silvina + Andy): work through tutorial problems using skills and concepts from previous lecture February 6, 2018 L01-10
27 Course Mechanics Three modules: Digital design: Combinational and sequential circuits (L1-7) Computer organization: Instruction sets, simple processor design, caches, virtual memory, and operating systems (L8-14) High-performance processors: pipelining and parallelism (L15-24) 2 lectures/week (Arvind + Daniel): handouts on website 2 recitations/week (Silvina + Andy): work through tutorial problems using skills and concepts from previous lecture 8 mandatory lab exercises Online submission + check-off meetings in lab Due throughout the term (7 free late days, see website) February 6, 2018 L01-10
28 Course Mechanics Three modules: Digital design: Combinational and sequential circuits (L1-7) Computer organization: Instruction sets, simple processor design, caches, virtual memory, and operating systems (L8-14) High-performance processors: pipelining and parallelism (L15-24) 2 lectures/week (Arvind + Daniel): handouts on website 2 recitations/week (Silvina + Andy): work through tutorial problems using skills and concepts from previous lecture 8 mandatory lab exercises Online submission + check-off meetings in lab Due throughout the term (7 free late days, see website) One open-ended design project Due at the end of the term February 6, 2018 L01-10
29 Course Mechanics Three modules: Digital design: Combinational and sequential circuits (L1-7) Computer organization: Instruction sets, simple processor design, caches, virtual memory, and operating systems (L8-14) High-performance processors: pipelining and parallelism (L15-24) 2 lectures/week (Arvind + Daniel): handouts on website 2 recitations/week (Silvina + Andy): work through tutorial problems using skills and concepts from previous lecture 8 mandatory lab exercises Online submission + check-off meetings in lab Due throughout the term (7 free late days, see website) One open-ended design project Due at the end of the term 3 quizzes: March 6, April 5, May 10, 19:30-21:30 If you have a conflict, contact us for makeup arrangements February 6, 2018 L01-10
30 Recitation Logistics Given the current enrollment, we will hold three out of the four planned recitation sections 11am, noon, and 1pm; contact us if you have conflicts February 6, 2018 L01-11
31 Recitation Logistics Given the current enrollment, we will hold three out of the four planned recitation sections 11am, noon, and 1pm; contact us if you have conflicts Registrar has not assigned recitation sections to most of you yet, so we will assign them: If you are happy with your current section, no action needed If you do not have a section or were assigned R04 (2pm), send your preferences to 6s084-staff@csail.mit.edu by 9pm today If we do not hear from you by 9pm, we will assume any section is fine We will reply with your final section assignment tonight, so you can attend the first recitation tomorrow February 6, 2018 L01-11
32 Grading 80 points from labs, 20 points from design project, 60 points from quizzes February 6, 2018 L01-12
33 Grading 80 points from labs, 20 points from design project, 60 points from quizzes No fixed grade cutoffs; 60% or more As has fixed grade cutoffs, 50-65% of students have received an A in previous terms February 6, 2018 L01-12
34 Online and Offline Resources The course website has up-to-date information and handouts: We will use Piazza extensively February 6, 2018 L01-13
35 Online and Offline Resources The course website has up-to-date information and handouts: We will use Piazza extensively We will hold regular office hours in the lab (room ) to help you with lab assignments, infrastructure, and any other questions Initial hours: Mon & Wed 3-6pm, Tue & Thu 7-10pm We will adjust hours based on your needs and preferences February 6, 2018 L01-13
36 Online and Offline Resources The course website has up-to-date information and handouts: We will use Piazza extensively We will hold regular office hours in the lab (room ) to help you with lab assignments, infrastructure, and any other questions Initial hours: Mon & Wed 3-6pm, Tue & Thu 7-10pm We will adjust hours based on your needs and preferences Combination Lock: February 6, 2018 L01-13
37 We Want Your Feedback! Your input is crucial to fine-tune this offering of the course and improve the full-scale rollout next term Periodic informal surveys Any time: us or post on Piazza February 6, 2018 L01-14
38 The Digital Abstraction
39 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, February 6, 2018 L01-16
40 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, Voltage Time February 6, 2018 L01-16
41 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, Digital systems represent and process information using discrete symbols Voltage Time February 6, 2018 L01-16
42 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, Digital systems represent and process information using discrete symbols Typically binary symbols (bits) Voltage Time February 6, 2018 L01-16
43 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, Digital systems represent and process information using discrete symbols Typically binary symbols (bits) Encoded using ranges of a physical quantity (e.g., voltage) Voltage Time February 6, 2018 L01-16
44 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, Voltage Time Digital systems represent and process information using discrete symbols Typically binary symbols (bits) Encoded using ranges of a physical quantity (e.g., voltage) Voltage 1 0 Time February 6, 2018 L01-16
45 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, Voltage Time Digital systems represent and process information using discrete symbols Typically binary symbols (bits) Encoded using ranges of a physical quantity (e.g., voltage) Voltage 1 0 Time February 6, 2018 L01-16
46 Analog vs. Digital Systems Analog systems represent and process information using continuous signals e.g., voltage, current, temperature, pressure, Voltage Time Digital systems represent and process information using discrete symbols Typically binary symbols (bits) Encoded using ranges of a physical quantity (e.g., voltage) Voltage 1 0 Time Digital systems tolerate noise February 6, 2018 L01-16
47 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Expected output: Frequency-equalized voltage signal Voltage Voltage Time Time February 6, 2018 L01-17
48 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time February 6, 2018 L01-18
49 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time Does output match expected output? February 6, 2018 L01-18
50 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time Does output match expected output? Not quite! February 6, 2018 L01-18
51 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time Does output match expected output? Not quite! Why or why not? February 6, 2018 L01-18
52 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time Does output match expected output? Why or why not? Noise Not quite! February 6, 2018 L01-18
53 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time Does output match expected output? Why or why not? Not quite! Noise Manufacturing variations February 6, 2018 L01-18
54 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time Does output match expected output? Why or why not? Not quite! Noise Manufacturing variations Components degrade over time February 6, 2018 L01-18
55 Example: Analog Audio Equalizer Input: Voltage signal representing sound pressure Filters Bass gain Mid gain Expected output: Frequency-equalized voltage signal Voltage Treble gain Voltage Time Time Does output match expected output? Why or why not? February 6, 2018 Not quite! Noise Manufacturing variations Components degrade over time L01-18
56 The Digital Abstraction Real World Manufacturing variations Noise Ideal Abstract World 0/1 Bits Volts or Amperes or Lumens Keep in mind that the world is not digital, we would simply like to engineer it to behave that way. In the end we must use real physical phenomena to implement digital designs! February 6, 2018 L01-19
57 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V TH volts February 6, 2018 L01-20
58 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH volts February 6, 2018 L01-20
59 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts February 6, 2018 L01-20
60 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts Not quite correct. Why? February 6, 2018 L01-20
61 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts Not quite correct. Why? Hard to distinguish V TH -ε from V TH +ε February 6, 2018 L01-20
62 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts Not quite correct. Why? Hard to distinguish V TH -ε from V TH +ε Attempt #2: V L V H volts February 6, 2018 L01-20
63 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts Not quite correct. Why? Hard to distinguish V TH -ε from V TH +ε Attempt #2: V V L interpreted as 0 V L V H volts February 6, 2018 L01-20
64 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts Not quite correct. Why? Hard to distinguish V TH -ε from V TH +ε Attempt #2: V V L interpreted as 0 V L V H V V H interpreted as 1 volts February 6, 2018 L01-20
65 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts Not quite correct. Why? Hard to distinguish V TH -ε from V TH +ε Attempt #2: V V L interpreted as 0 V L V L < V < V H Undefined V H V V H interpreted as 1 volts February 6, 2018 L01-20
66 Using Voltages Digitally Key idea: Encode two symbols, 0 and 1 (1 bit) Use the same convention for every component and wire in our digital system Attempt #1: V < V TH interpreted as 0 V TH V V TH interpreted as 1 volts Not quite correct. Why? Hard to distinguish V TH -ε from V TH +ε Attempt #2: V V L interpreted as 0 V L V L < V < V H Undefined V H V V H interpreted as 1? volts February 6, 2018 L01-20
67 Will This System Work? Valid 0 : V L -ε Digital device Noise V L +ε: not a valid signal Digital device Upstream device transmits a signal at V L -ε, a valid 0. Noise on the wire causes the downstream device to receive V L +ε, which is undefined. February 6, 2018 L01-21
68 Will This System Work? Valid 0 : V L -ε Digital device Noise V L +ε: not a valid signal Digital device Upstream device transmits a signal at V L -ε, a valid 0. Noise on the wire causes the downstream device to receive V L +ε, which is undefined. How can we address this? February 6, 2018 L01-21
69 Will This System Work? Valid 0 : V L -ε Digital device Noise V L +ε: not a valid signal Digital device Upstream device transmits a signal at V L -ε, a valid 0. Noise on the wire causes the downstream device to receive V L +ε, which is undefined. How can we address this? Output voltages should use narrower ranges, so that signal will still be valid when it reaches an input even if there is noise. February 6, 2018 L01-21
70 Noise Margins volts February 6, 2018 L01-22
71 Noise Margins Proposed fix: Different specifications for inputs and outputs volts February 6, 2018 L01-22
72 Noise Margins Proposed fix: Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH volts February 6, 2018 L01-22
73 Noise Margins Proposed fix: Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH Valid 0 V OL V OH Valid 1 volts VALID OUTPUT REPRESENTATIONS February 6, 2018 L01-22
74 Noise Margins Proposed fix: Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH Digital input: 0 V IL, 1 V IH Valid 0 V OL V OH Valid 1 volts VALID OUTPUT REPRESENTATIONS February 6, 2018 L01-22
75 Noise Margins Proposed fix: Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH Digital input: 0 V IL, 1 V IH VALID INPUT REPRESENTATIONS Valid 0 V OL V IL V IH V OH Valid 1 volts VALID OUTPUT REPRESENTATIONS February 6, 2018 L01-22
76 Noise Margins Proposed fix: Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH Digital input: 0 V IL, 1 V IH V OL < V IL < V IH < V OH VALID INPUT REPRESENTATIONS Valid 0 V OL V IL V IH V OH Valid 1 volts VALID OUTPUT REPRESENTATIONS February 6, 2018 L01-22
77 Noise Margins Proposed fix: Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH Digital input: 0 V IL, 1 V IH V OL < V IL < V IH < V OH VALID INPUT REPRESENTATIONS Valid 0 V OL V IL Undefined V IH V OH Valid 1 volts NOISE MARGINS VALID OUTPUT REPRESENTATIONS February 6, 2018 L01-22
78 Noise Margins Proposed fix: Different specifications for inputs and outputs Digital output: 0 V OL, 1 V OH Digital input: 0 V IL, 1 V IH V OL < V IL < V IH < V OH VALID INPUT REPRESENTATIONS Valid 0 V OL V IL Undefined V IH V OH Valid 1 volts NOISE MARGINS VALID OUTPUT REPRESENTATIONS A digital device accepts marginal inputs and provides unquestionable outputs (to leave room for noise). February 6, 2018 L01-22
79 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I f g February 6, 2018 L01-23
80 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f g February 6, 2018 L01-23
81 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) g February 6, 2018 L01-23
82 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g February 6, 2018 L01-23
83 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g(f(v I +ε 1 )+ε 2 ) g February 6, 2018 L01-23
84 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g(f(v I +ε 1 )+ε 2 ) g Digital systems: Noise is canceled at each stage ε 1 ε 2 V I f g February 6, 2018 L01-23
85 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g(f(v I +ε 1 )+ε 2 ) g Digital systems: Noise is canceled at each stage ε 1 ε 2 V I V I +ε 1 f g February 6, 2018 L01-23
86 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g(f(v I +ε 1 )+ε 2 ) g Digital systems: Noise is canceled at each stage ε 1 ε 2 V I V I +ε 1 f(v f I ) g February 6, 2018 L01-23
87 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g(f(v I +ε 1 )+ε 2 ) g Digital systems: Noise is canceled at each stage ε 1 ε 2 V I V I +ε 1 f(v f I ) f(v I )+ε 2 g February 6, 2018 L01-23
88 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g(f(v I +ε 1 )+ε 2 ) g Digital systems: Noise is canceled at each stage ε 1 ε 2 V I V I +ε 1 f(v f I ) f(v I )+ε 2 g(f(v I )) g February 6, 2018 L01-23
89 Digital Systems are Restorative Analog systems: Noise accumulates ε 1 ε 2 V I V I +ε 1 f(v f I +ε 1 ) f(v I +ε 1 )+ε 2 g(f(v I +ε 1 )+ε 2 ) g Digital systems: Noise is canceled at each stage ε 1 ε 2 V I V I +ε 1 f(v f I ) f(v I )+ε 2 g(f(v I )) g Intuitively, canceling noise requires active components February 6, 2018 L01-23
90 Voltage Transfer Characteristic Buffer: A simple digital device that copies its input value to its output V out Voltage Transfer Characteristic (VTC): Plot of V out vs. V in where each measurement is taken after any transients have died out. V in February 6, 2018 L01-24
91 Voltage Transfer Characteristic Buffer: A simple digital device that copies its input value to its output V out V OH V IH Voltage Transfer Characteristic (VTC): Plot of V out vs. V in where each measurement is taken after any transients have died out. V IL V OL V in V OL V IL V IH V OH February 6, 2018 L01-24
92 Voltage Transfer Characteristic Buffer: A simple digital device that copies its input value to its output V out V OH V IH Voltage Transfer Characteristic (VTC): Plot of V out vs. V in where each measurement is taken after any transients have died out. V IL V OL V in V OL V IL V IH V OH VTC must avoid the shaded regions (aka forbidden zones ), which correspond to valid inputs but invalid outputs. February 6, 2018 L01-24
93 Voltage Transfer Characteristic Buffer: A simple digital device that copies its input value to its output V out V OH V IH Voltage Transfer Characteristic (VTC): Plot of V out vs. V in where each measurement is taken after any transients have died out. V IL V OL V OL V IL V IH V OH V in Note: VTC does not tell you anything about how fast a device is it measures static behavior, not dynamic behavior. VTC must avoid the shaded regions (aka forbidden zones ), which correspond to valid inputs but invalid outputs. February 6, 2018 L01-24
94 Voltage Transfer Characteristic V out V OH V OL V in V IL V IH February 6, 2018 L01-25
95 Voltage Transfer Characteristic V out V OH V OL V in V IL V IH 1) Note the center white region is taller than it is wide (V OH -V OL > V IH -V IL ). Net result: device must have GAIN > 1 and thus be ACTIVE February 6, 2018 L01-25
96 Voltage Transfer Characteristic V out V OH V OL V in V IL V IH 1) Note the center white region is taller than it is wide (V OH -V OL > V IH -V IL ). Net result: device must have GAIN > 1 and thus be ACTIVE 2) Note the VTC can do anything when V IL < V IN < V IH February 6, 2018 L01-25
97 Combinational Devices A combinational device is a circuit element that has one or more digital inputs one or more digital outputs a functional specification that details the value of each output for every possible combination of valid input values a timing specification consisting (at a minimum) of a propagation delay (t PD ): an upper bound on the required time to produce valid, stable output values from an arbitrary set of valid, stable input values input A input B Output a 1 if at least 2 out of 3 of my inputs are a 1. Otherwise, output 0. output Y input C I will generate a valid output in no more than 2 minutes after seeing valid inputs February 6, 2018 L01-26
98 Combinational Devices Static discipline A combinational device is a circuit element that has one or more digital inputs one or more digital outputs a functional specification that details the value of each output for every possible combination of valid input values a timing specification consisting (at a minimum) of a propagation delay (t PD ): an upper bound on the required time to produce valid, stable output values from an arbitrary set of valid, stable input values input A input B Output a 1 if at least 2 out of 3 of my inputs are a 1. Otherwise, output 0. output Y input C I will generate a valid output in no more than 2 minutes after seeing valid inputs February 6, 2018 L01-26
99 Composing Combinational Devices A set of interconnected elements is a combinational device if each circuit element is combinational every input is connected to exactly one output or to a constant (0 or 1) the circuit contains no directed cycles February 6, 2018 L01-27
100 Composing Combinational Devices A set of interconnected elements is a combinational device if each circuit element is combinational every input is connected to exactly one output or to a constant (0 or 1) the circuit contains no directed cycles Why is this true? February 6, 2018 L01-27
101 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? A C B February 6, 2018 L01-28
102 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? A C B Does it have digital inputs? February 6, 2018 L01-28
103 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? A C B Does it have digital inputs? Yes February 6, 2018 L01-28
104 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? A C B Does it have digital inputs? Does it have digital outputs? Yes February 6, 2018 L01-28
105 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? A C B Does it have digital inputs? Does it have digital outputs? Yes Yes February 6, 2018 L01-28
106 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? A C B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? February 6, 2018 L01-28
107 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? X Y A C Z B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? February 6, 2018 L01-28
108 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? X Y A C W Z B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? February 6, 2018 L01-28
109 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? X Y A C W Z B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? W = f C (f A (X, Y), f B (f A (X, Y), Z) February 6, 2018 L01-28
110 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? X Y A C W Z B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? W = f C (f A (X, Y), f B (f A (X, Y), Z) Can you derive a t PD? February 6, 2018 L01-28
111 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? X Y A C W Z B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? W = f C (f A (X, Y), f B (f A (X, Y), Z) Can you derive a t PD? February 6, 2018 L01-28
112 Is This a Combinational Device? A, B and C are combinational devices. Is the following circuit a combinational device? X Y A C W Z B Does it have digital inputs? Yes Does it have digital outputs? Yes Can you derive a functional description? W = f C (f A (X, Y), f B (f A (X, Y), Z) Can you derive a t PD? t PD = t PD,A + t PD,B + t PD,C February 6, 2018 L01-28
113 Summary Digital encoding Valid voltage levels for representing 0 and 1 Undefined range avoids mistaking 0 for 1 and vice versa Gives rise to notion of signal VALIDITY February 6, 2018 L01-29
114 Summary Digital encoding Valid voltage levels for representing 0 and 1 Undefined range avoids mistaking 0 for 1 and vice versa Gives rise to notion of signal VALIDITY Noise margins require tougher standards for outputs than for inputs Means devices must have gain and have a non-linear VTC February 6, 2018 L01-29
115 Summary Digital encoding Valid voltage levels for representing 0 and 1 Undefined range avoids mistaking 0 for 1 and vice versa Gives rise to notion of signal VALIDITY Noise margins require tougher standards for outputs than for inputs Means devices must have gain and have a non-linear VTC Combinational devices Have Tinkertoy-set simplicity, modularity Predictable composition: parts work whole thing works Must obey static discipline Digital inputs & outputs; restores marginal input voltages Complete functional specification Valid inputs lead to valid outputs in bounded time February 6, 2018 L01-29
116 Thank you! Next lecture: Boolean algebra & binary arithmetic
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