An Efficent Real Time Analysis of Carry Select Adder

Transcription

1 An Efficent Real Time Analysis of Carry Select Adder Geetika Gesu Department of Electronics Engineering Abha Gaikwad-Patil College of Engineering Nagpur, Maharashtra, India Sagar Ghormade Department of Electronics Engineering Abha Gaikwad-Patil College of Engineering Nagpur, Maharashtra, India Abstract In order to obtain optimized level of power sustained with provided design to increase the speed in terms of integrated format of circuit. This paper presents performance analysis of 64-Bit CSLA. As worked upon the parameterized format of comparison of varied three efficient performances based on its area, provided speed and optimization of power. In this paper implementation of carry select adder improvised into design parameters of different level platforms. With the evaluations carried under the adder process has considerable reduction in are and optimized power trade off. Purpose of Carry Select Adder (CSLA) is proposed for efficient propagation in adder process with enhanced usage in processing of invariant data with speedy ALU based operations. Paper proposes a review into design aspect of gate enhanced modification format. As considered with method of design in terms of 64 bit CSLA architecture. Hence, this paper has the evaluation of process in terms of its work progress with block layout approached at 0.18µm CMOS technological update. Analysis of result is in review process with block implementation in terms of SoC RTOS embedded systems. Application specified Systems with low power VLSI traced and modeled with behavioral synthesis for CSLA. Keywords System On Chip Real Time Opearting Systems (SoC RTOS), Embedded System, low power, Very Large Scale Integartion(VLSI), Application-specific Systems, Reduced Area, Carry Select Adder (CSLA), low power, Behavioral synthesis. ***** I. INTRODUCTION Design based on the reduced area and optimization of power with recurrent analysis of comparative speed based design logics lead to most efficient real time analysis areas for low power VLSI. Comparative analysis is done in terms of design of adders with limitations prospered for propagation of relative carry with addition. When summation of bits in singular bit sequence is done with generation of carry along next bit parameters. Digital design synthesis has the use of Carry Select Adder (CSLA) to rectify the carry based propagation problem analysis by System On Chip (SoC) generation of distinct carries with Cin values and henceforth, selecting a specified carry to process the sum term[1]. Most of time this synthesis is not efficient with usage of numerous pairs multi-valued Ripple Carry based Adders (RCA) with generation of partial based sum and carry generation based on Multiplexer (MUX). Proposed work is synthesized with Binary based values evaluated with Excess-1 code converter (BEC) [2][4]. Thus, it optimizes the power consumption and reduced area level with application specified systems with lower implementation of logical gates in Full Adder structural logic synthesis. II. LITERATURE SURVEY A conventional carry select adder is a configuration of dual RCA in which one RCA generates sum and carry output by assuming Cin = 0and the other RCA produce carry and sum and sum assuming Cin = 1 [3]. This conventional carry select adder has less carry propagation delay than conventional RCA adder but increases the complexity due to dual RCA structure. A carry select adder generating carry of block with carry in as 1 from the block with carry in as 0 was proposed by Tyagi.A [4] in Later in 1998 T.Y.Ceiang and M.J.Hsiao [5] proposed a carry select adder consisting of single ripple carry adder. This was a real breakthrough in the carry select adder history. In 2001 a further modified carry select adder with increased delay but reduced area and power was presented by Kim and Kim [6]. Here the RCA section was replaced using an add one circuit using multiplexer (MUX). Later in the year 2005 a further modified carry select adder which reduces the area and power consumption was proposed by Amelifard B, Fallah F and Pedram.M [7]. Later a SQRT-CSLA was proposed by Chang C, et al [8] which helps proposed long bit sequence increased width with lower delay rate. This system the CSLA s with increasing bit widths are cascaded with each other. It helps in reducing the overall adder delay. A BEC based CSLA was further proposed by Ramkumar and Kittur [9] which had fewer resources than conventional CSLA but with more delay. A CBL (common Boolean logic) based CSLA [10] was also proposed which requires less logic resources but CPD (carry propagation delay) was similar to that of RCA. A CBL based SQRT CSLA [11] was also proposed but the design requires more logic resource and delay than BEC based SQRT CSLA. Now a further modification of CSLA called Area Delay-Power Efficient Carry Select Adder [12] was proposed. Here the carry generation is faster but the area consumption is not much reduced. The carry of the system is calculated before the sum generation. The carry generation unit was also replaced using an optimized logic. Thus the system has lesser carry output delay than all other system. Though the carry generation is faster, the area and power consumption are not much reduced. So a further modification with a reduction in area and power consumption, thus obtaining an optimized area-delay and power carry efficient carry select adder is proposed here. III. METHDOLOGY As the proposed methodology with the implementation of Carry Select Adder (CSLA) is a condition based adder with carry values having its input real time values design oriented sum and carry with use of multiplexer. Digital design logical analysis in terms of gates of logic based on AND, OR and 214

2 XOR [9] is approached in design of multiplexer (MUX) with IV. BINARY TO EXCESS-1 CONVERTED block CMOS verified along Programmable Gate Arrays. As stated implementation based on this work is Analysis performed with end states with end term bit valued utilization Binary with Excess-1 instead of array of gates stage is processed under selection of real time SoC values with having input to carry bit equals unity. With this replacement respect to carry and its sum done along selection under MUX of RCA is done with n+1 coded format for reduction of area identifier. With division of CSLA into four selection stages and lowered power consumption with optimized. Based on with operational enhancement provided below as in terms its structured analysis on design flow and provided table block preview in Figure 3. The CSLA is further divided as: - below with figure based blocks in terms of both figure 2 and 1) Half sum generator 3. Carry Select Adder is structured in behavioral format of 2) Carry generator modeling with use of 4 bit sequence based BEC with MUX 3) Carry selection having utilization of input bit sequence in priority from 3 4) Full sum generator. onwards to 0 (bit vector 3 down to 0) is required output With implementation of gate layouts in Figure 1 we have level. The parallel pipelined analysis in terms of its products optimized parallel pipelining and arbitrary valued iteration of and synthesis of MUX together leads to next level of gate level synthesis provided with certain delay. With selection of Binary and Excess-1 performed outputs with evaluation process considered gate level architecture in distinct input C (Carry) based signals. With proper Gate demonstration in Figure 2. Duration of delay element evaluated count estimated reduction in silicon area with propagates to one single unit of delay. This is considered in design flow of large blocks of Carry select Adders (CSLAs). terms of analysis with defined problem statement with summation in array of gates in sequence to assigned system with presence of delay. Thus, an implementation of previous type block of CSLA with Carry selection has either value 1or its varied bit 0 [2] [3]. With process of Adders and MUX contribute in reduction of area with optimized power enactment. Clock duration of design clock time of 1 clock duration with time based duration cycle evaluation. Analysis and calculation of sum total of System on Chip based application enabled real time system specified gates is done for every design analysis. A review analysis is considered for MUX and CSLA Design flow statements in terms of Half Adder and Full adder analysis as per Table I. The output of the half adder is given as input to the carry generator circuit. Two Table II: Comparison Table carry generator circuits are used in the design, CG0 and CG1. Demonstration of Analytical process in above Table II is CG0 is used to generate carry by assuming carry input as 0 and considered again and analyzed in the sequence of Array of CG1 is used to generate carry by assuming input carry as 1. adders with input sequence with MUX and further, overall Both CG and CG10 receives half carry word and half sum word delay is analyzed with reduction of area and optimized from the half adder and generation of design blocks of nth bit power effort parallel is obtained in terms of total 64-bit sequence full based carry in terms of words Carry Bit C from 1 sequence in Count of Carry Out bit sequences with regular to 0 and similarly from C bit 1 to 1. With bit input series from Square Root of Carry Select Adder. 0 and 1 respectively. C1 0(i) = C1 0(i-1)*S0 (i) + C0 (i) for V. SIMULATION RESULTS (C1 0(0) = (0) C1 1(i) = C1 1(i-1)*S0 (i) + C0 (i) for (C1 1(0) =1) Table I: Showing evaluation of Adder The proposed design is developed using VHDL and synthesized using XILINX 9.1i and is simulated in ISA Spartan-3e FPGA series. The Flow of respective block orientation in reviewed format of proposed plan in this paper design proposed in this paper uses HDL based CMOS block schematic synthesis using Real Time Logic based on Verilog duration of threshold value is estimated at 0.18 µm technological systolic analyses. Application Specified System RTL based System Design Constraint enabled files used to provide automated layout, with placement and routing of parallel paths[5] [7]. Extraction based tool of Encounter Native RC based extraction is evaluated with its parasitic counterpart with backward process of annotation of timing engine in common platform uses its static timing based analysis. Every adder based word size performed with value changed dump (VCD) formed in control to its possible all inputs having last iterations of varied Cadence Encounter Power Analysis. 215

3 VI. CONCLUSION REFERENCES This paper provides an efficient approach proposed for design and implementation reduce the area and delay of SQRT CSLA architecture. The reduction in the number of gates is obtained by simply replacing the RCA with BEC in the structure. The compared results shows that the enhanced version of 64-bit review of SQRT enabled Carry Select Adder has somewhat large area specified for lower bit sequence however, its vice-versa reduces for considerable large bits. Reduction delay tome with optimized power is greatly approached by Carry Select Adder. Thus the results shows that using modified method the area and delay will decrease thus leads to good alternative for adder implementation for many processors. This architecture therefore, provides low area and high speed approaches for VLSI hardware implementation, with considerable decrease in delay rate as shown in simulation waveforms form Figure 3 and 4 is obtained with optimized power approached with 64-bit design Carry Select Adder for consideration in Figure 5 for further proposed future prospects in terms of 128-bits and 256-bits respectively. [1] Bedrij, O. J., (1962), Carry-select adder, IRE Trans. Electron. Comput. Pp [2] Ramkumar,B., Kittur, H.M. and Kannan,P. M.,(2010 ), ASIC implementation of modified faster carry save adder, Eur. J. Sci. Res., vol. 42, no. 1,pp [3] Kim,Y. and Kim,L.-S.,(May2001), 64-bit carry-select adder with reduced area, Electron Lett., vol. 37, no. 10, pp [4] Ceiang, T. Y. and Hsiao. J., (Oct 1998), Carry-select adder using single ripple carry adder, Electron. Lett., vol. 34, no. 22, pp [5] He, Y., Chang, C. H. and Gu, J., (2005), An A rea efficient 64-bit square root carryselect adder for low power application, in Proc. IEEE Int. Symp.Circuits O. J. Bedrij, Carry-select adder, IRE Trans. Electron. Comput., pp , C. Perkins, E. Belding-Royer, S. Das. Ad hoc On-Demand Distance Vector (AODV) Routing. Feb [6] B. Ramkumar, H.M. Kittur, and P. M. Kannan, ASIC implementation of modified faster carry save adder, Eur. J. Sci. Res., vol. 42, no. 1, pp , [7] T. Y. Ceiang and M. J. Hsiao, Carry-select adder using single ripple carry adder, Electron. Lett., vol. 34, no. 22, pp , Oct [8] Y. Kim and L.-S. Kim, 64-bit carry-select adder with reduced area, Electron. Lett., vol. 37, no. 10, pp , May [9] J. M. Rabaey, Digtal Integrated Circuits A Design Perspective. Upper Saddle River, NJ: Prentice-Hall, Figure 1. Delay and Area evaluation. Figure 2. BEC Evaluation Process 216

4 Figure 3. Simulation Waveform-1 of Carry Select Adder Figure 4. Simulation Waveform-2 of three stage Carry Select Adder 217

5 Figure 5. Delay and Evaluation of entire proposed 64-bit logical adder 218