SQRT CSLA with Less Delay and Reduced Area Using FPGA

Transcription

1 SQRT with Less Delay and Reduced Area Using FPGA Shrishti khurana 1, Dinesh Kumar Verma 2 Electronics and Communication P.D.M College of Engineering Shrishti.khurana16@gmail.com, er.dineshverma@gmail.com Abstract: Carry select adder () is used to perform fast arithmetic operations in many data processing processors. It is also used in many computational systems to alleviate the problem of carry propagation delay by independently generating multiple carries and the select a carry to generate sum. Carry Select Adder consists of two ripple carry adder and multiplexer. This paper outlines the method to reduce the area and delay in the SQRT. Area and delay has been reduced by implying an efficient gate level modification. This paper has shown the comparison between 16, 32, 64 bit regular SQRT and 16, 32, 64 bit modified SQRT. The regular SQRT uses multiple pairs of Ripple carry adders to generate partial sum and carry by considering carry input Cin=0 and Cin=1, then the final sum and carry are selected by multiplexers and hence is not area efficient. In modified SQRT, Binary to Excess converter is used instead of RCA with cin=1 to achieve lower area and lower delay. Also, the performance of proposed designed is measured in terms of area, delay and synthesis are implemented in Xilinx ISE. The results analysis shows that the modified SQRT structure is better than the regular SQRT. Index terms:-field programmable logic device (FPGA), area efficient,, low delay. 1. INTRODUCTION Reduced area and high speed data path logic systems are the main area of research in VLSI system design. In digital adder, the speed of addition is limited by the time require to propagate a carry through the adder. The sum for each bit position in an elementary adder is generated sequentially only after the previous bit position has be summed and carry propagate into next position. Carry select adder () is the fastest adder used in data processing process to perform arithmetic function. The carry select adder is classified as linear and square root (SQRT).Linear is by chaining a number of equal length adder stages. For n-bit adder, it could be implemented with equal length of carry select adder. Linear does always have the best performance. SQRT is also known as nonlinear. It is constructed by equalizing the delay through two carry chains and the block multiplexer signal from previous stage. A has good performance in propagation delay especially the non-linear one, however it compensate with large area. The SQRT can be implemented in different length. The is used in many computational system to alleviate the problem of carry propagation delay by independently generating multiple carries and then select a carry to generate the sum [1]. It consists of two ripple carry adder (RCA) and a multiplexer (MUX). Adding two n-bit number with a carry select adder is done with two ripple carry adders in order to perform calculation twice one time with the assumption of carry being zero and other assuming carry one, then the final sum and carry are selected by the multiplexer(mux). However is not area efficient because it uses multiple pair of ripple carry adder (RCA). The basic idea of the work is to use binary to excess-1 converter (BEC) instead of RCA with cin=1 in regular to achieve lower area and lower delay[2]-[4]. The main advantage of this BEC logic comes from lesser number of logic gates. This work in brief is structured as follows. Section II deals with the delay and area equivalent methodologies of the basic adder blocks. Section III deal with structures and functions of BEC logic. Section IV presents the architecture of the regular and modified SQRT. Section V implementation methodology and finally work is concluded section IV. 2. DELAY AND AREA EQUIVALENT METHODOLOGY OF THE BASIC ADDER BLOCKS The AND, OR and Inverter (AOI) implement on the XOR gate. The delay area methodology all gates to be made up of AOI, each delay equal to 1 unit and area equal to 1 unit[5]. Add up the 94

2 numbers of gate in the longest path of logic that contribute maximum delay. The area evaluation is done by counting the total number of AOI required for each logic. Based on this approach the blocks of 2:1 MUX, half adder and full-adder are evaluated in table:- X3=B3^(B0&B1&b2) Fig 2:- 4-bit BEC Fig1:-delay and area equivalent of an XOR gate B[3:0] X[3:0] Table 1:-delay and area count of the basic block of Adder block Delay Area XOR 3 5 2:1 mux 3 4 Half adder 3 6 Full-adder BEC The basic work is to use binary to excess converter instead of the ripple carry adder. To replace the n- bit RCA an n+1 bit BEC is required. The work is to use binary to excess-1 converter in the regular to achieve lower area, delay, and increase the speed of operation. The regular used 2 ripple carry one for cin=0 and another for cin=1. The cin=1 RCA is replaced by BEC. In fig show the basic function of the is obtained by using a 4-bit BEC.The Boolean expression of the 4-bit BEC is X0= ~B0 X1=B0^B1 X2=B2^(BO&B1) Table 2:-function table of 4-bit BEC 4. ARCHITECTURE OF REGULAR AND MODIFIED SQRT a) Regular 16 bit SQRT Carry select adder generally consist of two ripple carry adder one for cin=0 and another for cin=1. In fig we have shown the regular structure of 16-bit SQRT. Regular 16-bit SQRT uses multiple pairs of ripple carry adder by considering carry input cin=0 and other cin=1. For cin=0, we have used half adder and full adder and cin=1 used full adder. Regular 16-bit SQRT includes many ripple carry adders of variable sizes which are divided into groups. It has five groups of different size RCA. Fig 3 shows the regular structure of 16-bit SQRT. Group 1 contains 2-bit RCA which contains only one ripple carry adder which adds the input bits, input carry and result, sum and carry. The 2 bit input of A and B and 1 bit input is cin. The ripple carry adder adds the bits, it has used two fulladders. In regular there is only one RCA to perform addition of the least significant bits [1:0]. The remaining bits, the addition is performed by using a two ripple carry adders in order to perform calculation twice one time with the assumption of 95

3 carry being zero and other assuming carry one, then the final sum and carry are selected by the multiplexer (mux). Group 2 to group 5:- In a group, there are two RCA that receive the same data input but different cin. The upper adder for cin=0, the lower adder a cin=1. The cin=0, the sum and carry-out of the upper RCA selected and if cin=1, the sum and carry-out of the lower RCA is selected. The cin=0 used one half adder for the 1 st bit of that RCA and another bits used full adder. The cin=1 used full adders. b) Modified 16 bit SQRT The architecture is similar to regular 16-bit SQRT, the only change is that, it used binary to excess-1 converter(bec) instead of RCA with cin=1 in the regular to achieve lower area delay and power consumption. The number of bits Fig3:-architecture of regular 16 bit SQRT 96

4 Fig 4 :-group 1 to 5 16 bit SQRT required for BEC is 1 bit more than the RCA bits.the modified SQRT is also divided into various groups. Each groups having the RCA, BEC and mux. The XOR gate in BEC of modified is replaced with the optimize XOR gate in AOI. The optimize XOR gate is used in modified it is verify that large Fig 5:-architecture of modified 16-bit SQRT \ 97

5 multiplexer(mux). The design code for the BEC was designed by using NOT, AND and XOR gates. c) Regular 32-bit SQRT reduction in no of gates. The advantage of this BEC logic comes from lesser number of logic gates. It has 5 groups of different size RCA. Group 1 contains 2-bit RCA which contains only one ripple carry adder which adds the input bits, input carry and result, sum and carry. The 2 bit input of A and B and 1 bit input is cin. In modified there is only one RCA to perform addition of the least significant bits[1:0]. The remaining bits, the addition is performed by using a one ripple carry adder and binary to excess converter, then the final sum and carry are selected by the Fig 6:- group 2 to 5 of modified 16 bit SQRT RCA and one mux [6]. The 8 groups are same as 32-bit, the 9 groups contain 9-bit [40:31], the group 10 contains 10 bit [51:41] and the group 11 contains 11 bit [63:52]. The regular 32-bit SQRT is same as 16-bit, only the number of bits has increased. It consists of 8-block two RCA and one mux. It has 8 groups. The 5 groups are same as 16-bit. The 6 groups contain 7-bit [21:16], the group 7 contains 8-bit [28:22] and the group 8 contains 3 bit [31:29]. d) Modified 32-bit SQRT The modified 32-bit SQRT is same as regular, the only change is that used BEC instead of RCA with cin=1 in the regular to achieve lower area and delay. e) Regular 64-bit The 64-bit is same as 32-bit, only the number of bits is increased. It has 11 groups which consists of 3-block two Table 3:-Area and delay of 16-b regular SQRT f) Modified 64-bit SQRT The modified 64-bit SQRT is same as regular, the only change is that used BEC instead of RCA with cin=1 in the regular to achieve lower area and delay. 5. RESULTS Table 4:-Area and delay of 16-b modified SQRT The implementation design in this work has been stimulated using Verilog-HDL (modelsim). The adders of various size 16, 32 and 64 are designed and stimulate using modelsim. After stimulation the different size codes are synthesized using Xilinx ISE The synthesized report contains area and delay values for different adders. Table 5:-Area and delay of 32-b regular SQRT 98

6 REFERENCE Table 6:-Area and delay of 32-b modified SQRT [1]. O.J. Bdergi carry select adder IRE trans electron. Computt,pp , [2]. B.Ramkumar, H.M. Kittur and P.M.kannan, ASIC implementation of modified faster carry save adder, Eur.J.sci.Res., vol42, no.1 pp.53-58,2010. [3]. T.Y. ceiang and M.J.Hsiao, carry select adder using single ripple carry adder electron. lett, vol34, no22, pp , oct [4]. Y. Kim and L.S Kim, 64 bit carry select adder with reduce area, electron let.,vol 37,no 10,pp may [5]. B.Ramkumar and HarishM kittur, low power and area efficient IEEE trans, vol 20, pp feb [6]. K.Allipeera and S Ahmed Basha, an efficient 64-bit Carry select adder with less delay and reduce area application intenational journal, vol 2, pp , oct Table 7:-Area and delay of 64-b regular SQRT Table 8:-Area and delay of 64-b modified SQRT 6. CONCLUSION A simple approach is proposed in this paper to reduce the area and delay of SQRT. The compared results show the modified SQRT has less delay and reduce area. The reduction in number of gates is obtained by simply replacing the RCA with BEC in the structure. The modified architechure is therefore low area, less delay, simple and efficient for VLSI hardware implementation. It would be interested to test the design of the modified 128-b SQRT. 99