# DIGITAL INTEGRATED CIRCUITS FALL 2003 ANALYSIS AND DESIGN OF DIGITAL INTEGRATED CIRCUITS (18-322) COURSE SYLLABUS

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1 ANALYSIS AND DESIGN OF DIGITAL INTEGRATED CIRCUITS (18-322) COURSE SYLLABUS Prof. Herman Schmit HH 2108; x Prof. Andrzej J. Strojwas HH 2106; X

2 I. PURPOSE Analysis and Design of Digital Integrated Circuits (18-322) is intended to provide the electrical and computer engineering student with a familiarity to and an understanding of the analytical and computer skills required for the analysis, computer simulation, design, and computer-aided physical layout of digital integrated circuits, and the capacity to apply this knowledge with creative skill to a variety of applications in electrical and computer engineering. Analysis and Design of Digital Integrated Circuits (18-322) is preparatory for study in the field of Very Large Scale Integrated (VLSI) digital circuits and engineering practice. The course focuses upon the systematic analysis and design of basic digital integrated circuits in CMOS technology, with a brief description of BiCMOS integrated circuit technologies. Problem solving and creative circuit design techniques are emphasized throughout. II. COURSE OBJECTIVES The objectives of Analysis and Design of Digital Integrated Circuits (18-322) are for the electrical and computer engineering student to learn how to model, analyze, simulate, and design digital integrated circuits for engineering applications. These circuits can be comprised of independent voltage and current sources, linear circuit elements (resistors and capacitors), and MOSFET and/or bipolar transistors. The circuits are characterized under constant (dc) and pulse (transient) excitations. Analysis and Design of Digital Integrated Circuits (18-322) provides the foundation for subsequent courses in the design of digital integrated circuits and systems, and for electrical and computer engineering practice. Basic principles, methodologies, and ad hoc analysis and design techniques are emphasized. Specifically, Analysis and Design of Digital Integrated Circuits (18-322) is intended: (1) To provide the electrical and computer engineering student with a working knowledge of digital integrated devices, circuits, and properties. (2) To develop an understanding of the static and transient characteristics of digital integrated devices and circuits. (3) To introduce the principles of combinatorial and sequential digital integrated circuits. (4) To introduce the principles of digital integrated memory circuits and systems. (5) To introduce BiCMOS digital circuits. (6) To develop the student s ability to design a small chip using both synthesis-based and custom design flows. 2

3 (7) To develop the student's ability to simulate the electrical characteristics of digital integrated circuits using the SPICE program. (8) To develop the student's ability to simulate the logic functions of digital integrated circuits using the CADENCE VERILOG tools. (9) To develop the student's ability to recognize and synthesize the physical layout of digital integrated circuits using the CADENCE VIRTUOSO layout tools. III. COURSE CONTENTS The topics to be covered in Analysis and Design of Digital Integrated Circuits (18-322) are: An introduction to the fundamental principles, ideas, and methodologies for the analysis, simulation, and design of digital integrated circuits. Emphasis is on the analysis and design of CMOS, digital integrated circuits using DC and transient analysis techniques. Junction diode, MOSFET, and BJT characteristics; CMOS static inverter analyses; CMOS, inverter delay analyses; CMOS combinatorial and sequential gates; BiCMOS Circuits; MOS memory circuits and systems; SPICE circuit simulation techniques; VERILOG logic simulation techniques; CADENCE VIRTUOSO computer-aided physical layout techniques, RTL description of CMOS logic circuits for semi-custom design. IV. PLAN OF THE COURSE The subject matter of Analysis and Design of Digital Integrated Circuits (18-322) may be divided into 8 categories. (A Tentative Lecture and Examination Schedule is on page 8 of this Course Syllabus.) The categories and the approximate time to be devoted to each are: (1) Introduction to CMOS Circuit Design & Fabrication Process... 2 weeks (2) CMOS physical layout and CADENCE/Semi-custom design... 2 weeks (3) Interconnects... 1 week (4) CMOS combinatorial and sequential gates... 2 weeks (5) Low Power Design... 1 week (6) Introduction to CMOS Processes... 1 week (7) MOSFET and bipolar device characteristics... 1 week (8) Analysis of static CMOS Gates week (9) Delay Analysis... 1 week 3

4 (10) BiCMOS Technologies week (11) MOS memory circuits and systems... 1 week (12) Future trends in VLSI/ULSI Design and Manufacturing... 1 week V. READING MATERIALS TEXT: Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective. Second Edition, Prentice- Hall, 2003, ISBN VI. GRADING SYSTEM Final course grades will be computed according to the following: Tests (1) 20 % Final Examination (2) 30 % Labs (3) 30 % Homeworks (4) 20 % NOTES (1) The tests will be given on Tuesday, October 14 th and Tuesday, November 18 th. The tests and final examination are closed textbook and notes. The first test will cover material up to and including October 2nd. The second test will cover material presented up to and including the lecture on November 4 th. The final examination will be comprehensive. (2) The schedule for the closed-book final examination will be announced by the registrar. (3) Minimum requirements for the laboratory reports will be clearly specified by the TA. The grading breakdown for each individual lab will be given in advance as a part of the lab handouts. Attendance in each lab is mandatory. Laboratory projects will vary in duration from 1 to 6 weeks and will be assigned in accordance with the Tentative Laboratory Schedule on page 9 of this Course Outline. (4) Homework assignments will normally be due one week after assignment. A Tentative Homework Schedule is given on page 10 of this Course Outline. (5) MAKE-UP POLICY -- Only in cases of extenuating circumstances, to be approved by the course instructors in advance, will a student be allowed to make-up a missed test or 4

5 laboratory project report. When an apparent extenuating circumstance arises, the student must make every effort to inform the course instructors in advance of the test or laboratory report deadline. The make-up procedures for such omissions will be determined on an individual basis. VII. CHEATING AND PLAGIARISM Students are referred to the University Policy About Cheating and Plagiarism. The policy of this course will be to discourage cheating to the extent possible. Students caught cheating will be disciplined in accordance with the Department of Electrical and Computer Engineering and CMU policies. Students are encouraged to discuss assignments with one another. Unless otherwise specified, the material submitted for grading, however, must be the product of individual effort. VIII. CLASS SCHEDULE LECTURES Prof. Andrzej J. Strojwas and Prof. Herman Schmit (HH 2106: X83530) (HH 2108; X86470) Lecture TH 3:00 PM 4:20 PM DH 2210 RECITATIONS Recitation 1: F 10:30 11:20 AM Reed Taylor SH 224 Recitation 2: M 10:30 AM - 11:20 AM Vikas Chandra SH 422 Recitation 3: M 11:30 AM - 12:20 AM Slava Rovner BH 235B Note: Recitation sessions will begin with Recitation 1 on September 5,

6 LABORATORIES Section A: Vikas Chandra & T 6:30 PM - 9:20 PM Zachary Menegakis HH 1107 Section B: Reed Taylor & W 6:30 PM - 9:20 PM Rebecca Miller HH 1107 Section C: Slava Rovner & R 6:30 PM - 9:20 PM Zachary Menegakis & HH 1107 Rebecca Miller Note: Laboratory sessions will begin with Section A on September 2,

7 IX. OFFICE HOURS Professor Andrzej J. Strojwas Wednesday 4:00 to 6:00 pm HH 2106: X in office Professor Herman Schmit Wednesday 4:00 to 6:00 pm HH 2108: X in office TA s (In Computer Cluster HH1107) Vikas Chandra day/tba time/tba Zachary Menegakis day TBA time/tba Rebecca Miller day TBA time/tba Slava Rovner day TBA time/tba Reed Taylor day TBA time/tba Yaping Zhan (grader) day TBA time/tba Course Secretary Judy Bandola HH 2107: X :00 am 4:30 pm THE WEB PAGE FOR THE 322 CLASS IS: 7

8 TENTATIVE LECTURE AND EXAMINATION SCHEDULE LECTURE DATE SUBJECT 1 Tue., 26 Aug. Introduction to CMOS Circuits. VLSI Design Flow 2 Thurs., 28 Aug. Basic CMOS Logic Design 3 Tue., 2 Sept. Introduction to CMOS Process: From Circuit to Silicon 4 Thurs., 4 Sept. MOSFET Device Model for Circuit Simulation 5 Tue., 9 Sept. Layout I: Custom Design Flow/CADENCE VIRTUOSO 6 Thurs., 11 Sept. Layout II: Floorplanning/Place & Route 7 Tue., 16 Sept. Transistor Sizing: Logical Effort 8 Thurs., 18 Sept. Interconnects I 9 Tue., 23 Sept. Registers 10 Thurs., 25 Sept. Registers, Clocks, and Clocking Schemes 11 Tue., 30 Sept. Interconnects II/Buffering techniques 12 Thurs., 2 Oct. Automatic Synthesis Design Flow/RTL 13 Tue., 7 Oct. CMOS Power Consumption/Low Power Design 14 Thurs., 9 Oct. Alternative Design Styles Tue., 14 Oct. EXAM I 15 Thurs., 16 Oct. CMOS Processes I 16 Tue. 21 Oct. CMOS Processes II 17 Thurs., 23 Oct. Device Modeling I (MOSFET) 18 Tue., 28 Oct. CMOS Gates: Sizing, VTC and Delay 19 Thurs., 30 Oct. CMOS Inverter: VTC and Delay 20 Tue., 4 Nov. Device Modeling II (BJT) & BJT Inverter 21 Thurs., 6 Nov. BiCMOS Circuits 22 Tue., 11 Nov. Overview of Semiconductor Memories 23 Thurs., 13 Nov. SRAM, DRAM and Flash Memories Tue., 18 Nov. EXAM II 24 Thurs., 20 Nov. VLSI Testing 25 Tue., 25 Nov. Big Project Review Thurs., 27 Nov. THANKSGIVING 26 Tue., 2 Dec. VLSI Design Trends. Final Project Results Review 27 Thurs., 4 Dec. VLSI Technology Trends. Final Exam Review/ Discussions 8

9 TENTATIVE LABORATORY SCHEDULE LABORATORY L1 - VERILOG Analysis and Design (1 week) Week of: 09/01 L2 - SPICE Analysis and Design (1 week) Week of: 09/08 L3 - VIRTUOSO and custom layout design (2 weeks) Weeks of: 09/15 & 9/22 L4 - Big Design Project (10 weeks) A: 09/30 D: 12/06 Synthesized Design: From RTL to Physical Design D: 10/07 Circuit Design and SPICE Verification (pre-layout) D: 10/31 VIRTUOSO layout design and verification D: 11/14 Final Project (Optimized Design) D: 11/25 Final report D: 12/05 9

10 TENTATIVE HOMEWORK SCHEDULE Assigned Due Date Topic 1 September 4 September 11 CMOS Logic Gates 2 September 11 September 18 MOSFET Characteristics 3 September 18 September 25 Transistor Sizing-Logical Effort 4 September 25 October 2 Interconnect I and Sequential Circuits 5 October 2 October 9 Interconnect II and RTL 6 October 16 October 23 CMOS Power & Alternative Design Styles 7 October 23 October 30 CMOS Cross Sections 8 October 30 November 6 MOSFET Inverters & Gates 9 November 6 November 13 CMOS Gates and Delay 10 November 13 November 20 BiCMOS Circuits. Memories 10

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