Lecture 12 - Digital Circuits (I) The inverter. October 20, 2005

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1 Microelectronic Devices and Circuits - Fall 25 Lecture 12-1 Lecture 12 - Digital Circuits (I) The inverter October 2, 25 Contents: 1. Introduction to digital electronics: the inverter 2. NMOS inverter with resistor pull up Reading assignment: Howe and Sodini, Ch. 5,

2 Microelectronic Devices and Circuits - Fall 25 Lecture 12-2 Key questions What are the key figures of merit of logic circuits? How can one make a simple inverter using a single MOSFET?

3 Microelectronic Devices and Circuits - Fall 25 Lecture Introduction to digital electronics: the inverter In digital electronics, digitally-encoded information is represented by means of two distinct voltage ranges: V AX V OH V OL IN logic 1 undefined region logic logic : IN V V OL logic 1: V OH V AX undefined logic value: V OL V V OH. Logic operations are performed using logic gates. Simplest logic operation of all: inversion inverter

4 Microelectronic Devices and Circuits - Fall 25 Lecture Ideal inverter: IN IN OUT=IN 1 OUT 1 Circuit representation and ideal transfer function: v+ V + = V = V+ 2 V + Define switching point or logic threshold: : input voltage for which V OU T = -for V OU T = V + -for V + V OU T =

5 Microelectronic Devices and Circuits - Fall 25 Lecture 12-5 Key property of ideal inverter: signal regeneration v + V+ = V VIN - - = V + 2 V+ Ideal inverter returns well defined logical outputs ( or V + ) even in the presence of considerable noise in (from voltage spikes, crosstalk, etc.) V + V + logic level el restoration V + V + noise suppression V + V + pulse edge sharpening

6 Microelectronic Devices and Circuits - Fall 25 Lecture Real inverter: logic 1 V + slope=-1 AX v+ V OH undefined region logic V OL IN A v >1 V In a real inverter, valid logic levels defined as follows: logic : IN output voltage when = V + V OL smallest output voltage where slope=-1 logic 1: V OH largest output voltage where slope=-1 AX output voltage when =

7 Microelectronic Devices and Circuits - Fall 25 Lecture 12-7 Two other important voltages: A v <1 noise suppressed logic 1 AX V OH slope=-1 undefined region logic A v >1 edges sharpened A v <1 V OL noise suppressed IN VIL V IH V + range of input values that produce acceptable logic 1 range of input values that produce acceptable logic V IL smallest input voltage where slope=-1 V IH highest input voltage where slope=-1 To have signal regeneration: range of input values that produce acceptable logic output > range of valid logic values Key to signal regeneration in inverter: high voltage gain

8 Microelectronic Devices and Circuits - Fall 25 Lecture 12-8 Quantify signal regeneration through noise margins. Consider chain of two inverters: M noise N VIN AX V OH NM H AX V IH VOL IN NM L V IL IN inverter M output Define noise margins: inverter N input NM H = V OH V IH NM L = V IL V OL noise margin high noise margin low When signal is within noise margins: logic 1 output from first inverter interpreted as logic 1 input by second inverter logic output from first inverter interpreted as logic input by second inverter

9 Microelectronic Devices and Circuits - Fall 25 Lecture 12-9 Simplifications for hand calculations Hard to compute A v = 1 points in transfer function. Approximate calculation: V OH =AX slope= A v ( ) = V OL =IN V IL V IH V + Assume V OL IN and V OH AX Trace tangent of transfer function at (slope=small signal voltage gain at ) V IL intersection of tangent with V OU T = AX V IH intersection of tangent with V OU T = IN to enhance noise margin: A v ( )

10 Microelectronic Devices and Circuits - Fall 25 Lecture 12-1 V OH =AX slope= A v ( ) = V OL =IN V IL V IH V + AX AX A v ( ) V IL V IL Av ( ) IN 1 IN A v ( ) V IH (1 + Av ( ) ) V IH A v ( ) Then: 1 NM L = V IL V OL (AX IN ) (AX )(1+ ) A v ( ) 1 NM H = V OH V IH (AX IN ) ( IN )(1+ A v ( ) ) If A v ( ) : NM L IN NM H AX

11 Microelectronic Devices and Circuits - Fall 25 Lecture Transient characteristics Look at inverter switching in the time domain: 9% V OH IN OUT 5% 1% V OL t t R t F t PHL t PLH V OH 9% 1% 5% t F t R t t CYCLE V OL t R rise time between 1% and 9% of total swing t F fall time between 9% and 1% of total swing t PHL propagation delay from high-to-low between 5% points t PLH propagation delay from low-to-high between 5% points Propagation delay: t P = 1 2 (t PHL + t PLH )

12 Microelectronic Devices and Circuits - Fall 25 Lecture Propagation delay: simplification for hand calculations Input wavefunction = ideal square wave Propagation delay times = delay times to 5% point V OH t CYCLE V OL t t PHL t PLH VOH V OH V OL 5% t CYCLE t Hand calculations only approximate SPICE essential for accurate delay analysis

13 Microelectronic Devices and Circuits - Fall 25 Lecture NMOS inverter with resistor pull up V + =V DD R I R I D C L load capacitance (from following stages) Features: V BS = (typically not shown) C L summarizes capacitive loading of following stages (other logic gates, interconnect lines) Basic operation: if <V T, MOSFET OFF = V DD if >V T, MOSFET ON small (value set by resistor/nmos divider)

14 Microelectronic Devices and Circuits - Fall 25 Lecture V DD + R I R V R - VOUT I D Transfer function obtained by solving: I R = I D Can solve graphically: I-V characteristics of pull-up resistor on I D vs. V OU T transistor characteristics: I R =I D I R =I D I R =I D V DD R V DD R 1/R 1/R 1/R V R =V DD - -V DD VR -V DD =-V OUT V DD

15 Microelectronic Devices and Circuits - Fall 25 Lecture Overlap I-V characteristics of resistor pull-up on I-V characteristics of transistor: I R =I D load line V DD V GS =V DD R V GS = V GS =V T V DD V DS = Transfer function: =V DS V DD V T V DD =V GS

16 Microelectronic Devices and Circuits - Fall 25 Lecture Logic levels: =V DS AX =V DD = IN V T V DD =V GS For AX, transistor is cut-off, I D =: AX = V DD For IN, transistor is in linear regime; solve: W IN V DD IN I D = µ n C ox (V DD V T )IN = I R = L 2 R For, transistor is in saturation; solve: I D = W µ n C ox ( V T ) 2 = I R = V DD 2L R Will continue next lecture with analysis of noise margin and dynamics...

17 Microelectronic Devices and Circuits - Fall 25 Lecture Key conclusions Logic circuits must exhibit noise margins in which they are inmune to noise in input signal. Logic circuits must be regenerative: able to restore clean logic values even if input is noisy. Propagation delay: time for logic gate to perform its function. Concept of load line: graphical technique to visualize transfer characteristics of inverter. First-order solution (by hand) of inverter figures of merit easy if regimes of operation of transistor are correctly identified. For more accurate solutions, use SPICE (or other circuit CAD tool).

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