Four-Way Traffic Light Controller Designing with VHDL

Transcription

1 Four-Way Traffic Light Controller Designing with VHDL Faizan Mansuri Viraj Panchal Department of Electronics and Communication,Institute of Technology, Nirma University Ahmedabad,Gujarat,India Abstract The simple traffic light controller design project was introduced to alleviate this shortcoming and gain experience in solving implementation and interfacing problems of a modern digital system. we implement a fully functional traffic signal controller for a four-way intersection. Intersection is complete with sensors to detect the presence of vehicles waiting at or approaching the intersection.these include VHDL for modeling and finite state machines, serial communication, and uploading the VHDL design code on ALTERA kit for verification of design Introduction Traffic lights, also known as traffic lamps, traffic signals, stoplight, stop-and-go lights semaphore or robots, are signaling devices positioned at pedestrian crossings, road intersections, and other locations to control competing flows of traffic. Traffic lights have installed in most cities around the world to control the flow of traffic. It assign the right of way to road users by the use of lights in standard colors (Red - Yellow - Green), using a universal color code (and a precise sequence, for color blind). Traffic lights are used at busy intersections to more evenly apportion delay to the various users. The increasing amount of traffic in the cities has a large impact on the congestion and the time it takes to reach a certain destination. But not only the amount of traffic but also how you deal with this traffic has a large impact. Adding roads is not sufficient by itself, since they will always reach an end point, like junction or bottlenecks. Bottlenecks cannot be prevented. However the way junctions are controlled has a lot of room for improvement. Junctions are controlled; it is mostly done by traffic lights. Traffic lights though, are most of the time not adaptive. The classic traffic light controller has a fixed-cycle which does not take in account how much traffic comes from any direction; it just switches configurations of lights on a timer interval. It often causes road users to wait at a completely empty junction with only one road user waiting for a red sign. Improvements already have been made, by putting sensors in the lanes in front of the traffic lights to let the controller only cycle between occupied lanes, thus disabling the chance of having to wait at a red light at an empty junction. More theoretical approaches to improve the traffic light control include machine learning algorithms. Machine Learning algorithms store the sensor information the sensors gather about the road users crossing the junction. This stored sensor information samples provide a way to predict the future driving behavior of road users and therefore enable the traffic light controller to calculate future waiting times for those road users for each action the traffic light controller can make. When the controller has the actions combined with waiting times, the optimal action would be to do one of these actions where the expected waiting times are the lowest. In the real world it is not realistic to assume that all the information can be gathered or that the gathered information is 100% accurate. Thus decisions have to be made based on incomplete or erroneous information. This implies working with partial observability. The used simulator has a discreet grid-like state space representation of the whereabouts of all road users. Running the simulator generates data this data exists of road users moving from one grid point to another.in this paper we have worked with simple four-way traffic light controller having sensor to detect vehicles at the intersection of

2 street. According to sensor input our design will work.we have discussed this in detail in our design portion.we have also done simulation of our VHDL design code in Quartus3.1 by ALTERA and generate a optimized hardware of our project. Traffic-Light Controller Design This project describes a simple traffic light controller design project for a junior level digital systems class at the Nirma University. It is developed because there was a need for laboratory exercises that incorporated microprocessors, simulation, VHDL modeling, serial communications,and a variety of related topics into a complete digital system. It requires students to develop a state machine based controller for traffic signals at a fourway intersection. This intersection has two travel lanes in each direction; east, west, north and south. In addition, each direction has a dedicated left turn lane. Each street i.e. NS(North-South) and EW(East-West) has a sensor to indicate presence of car at the intersection or if cars are approaching the intersectionthis project stresses the difference of writing VHDL for modeling and synthesis and that VHDL should not be thought of as a programming language. It gives proper design of combinational and sequential circuits. It requires proper definition of pin constraints for interfacing peripherals external to the FPGA or CPLD. Another drawback is that the study of components often occurred only in simulation. This led to confusion on how to write synthesizable VHDL.In this project we have used Quartus8.1 by ALTERA to design a traffic light controller using VHDL.We have used behavioural type Modeling to design sothat we can design only from state of outputs and inputs and we can get optimized hardware.after simulation we have verified our design on ALTERA kit using serial/parallel communication. Traffic-Signal Phase Sequences The traffic light controller must handle a fourphase signal intersection. If we consider only straight way direction when NS street is on then traffic is followed by North to South or South to North alternatively.during this EW street traffic is stopped by Red signal. After completion of NS street now EW street traffic is followed by East to West or West to East alternatively.if we considered another CLK possibility to follow traffic in another direction rather than straightway direction, we can see from fig.1 that during NS street on vehicles can go to left or right direction according to North-South direction parallelly to main direction because EW street is OFF during this.similarly we can say about EW street.. Fig.1:phase options Design Implementation A traffic light at the intersection of northsouth(ns) and east-west(ew streets goes through the following cycles of states : both red(5 sec), NS green (30 sec), NS yellow(5 s) -- both red(5s) EW green(30 sec) EW yellow (5sec).A 0.2 Hz clock signal is available for timing. Both streets are equipped with sensors that detects the presence of a car close to the intersection.whenever there is a car close to the intersection on the street currently having its light red while there is no car approaching the intersection on the street with green light, the switchover takes place and green light immediately turns to yellow. Block digram/flow diagram Counter RESET R Controller CONTROLLER State State Machine Y Machine G Fig.2 L E D D I S P L A Y

3 Acknowledgement We would like to thank our mentor Prof.Vijay Savani to give us this opportunity to make practical application of Digital System using VHDL code and for his motivation towards VHDL design implementation. Appendix We have attached VHDL source code of Traffic-light controller design, simulation result, RTL viewer and Technology Map Viewer. Simulation has been done in QURTUS II by ALTERA. Conclusion We have designed full system of Traffic-Light Controller by implementing the logic of block diagram of the system and could simulate the result on LED 7-segment display using counter and switchover of LED during this counter interval. We have also generated a optimized hardware using VHDL code and respective technology map viewer using QUARTUS II by ALTERA. After design we verified design using ALTERA kit having EPMT100C5 chip. References 1) Behrooz Parahami, Computer Architecture from Microprocessors to Supercomputers. 2)Charles H.Roth,Jr. and Lizy Kurian John, Digital System design using VHDL

4 Appendix Source Code: -- DSD PROJECT " 4 way traffic controller " -- Problem Statement: A traffic light at the intersection of north-south(ns) and east-west(ew) -- streets goes through the following cycles of states : both red(5 sec), NS green (30 sec), NS yellow(5 s) -- both red(5s) EW green(30 sec) EW yellow (5sec). -- A 0.2 Hz clock signal is available for timing. Both streets are equipped with sensors that detects -- the presence of a car close to the intersection.whenever there is a car close to the intersection on -- the street currently having its light red while there is no car approaching the intersection --on the street with green light, the switchover takes place and green light immediately turns to yellow. -- Design a sequential circuit for this traffic controller. -- Started date 12/02/ bec024 and 11bec047 --library declaration library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; --entity declaration entity dsd_project is port(t,clk,sensor1,sensor2:in std_logic; presetn :in std_logic; enable: out STD_LOGIC_VECTOR(3 downto 0); seg7 : out STD_LOGIC_VECTOR(6 downto 0);

5 g1,y1,r1,g2,y2,r2: buffer std_logic ); end entity; -- architecture declaration architecture trafficlightcontroller of dsd_project is signal count : std_logic_vector(3 downto 0); signal a,b,c,d:std_logic; signal temp:std_logic_vector(2 downto 0); begin counter:process(clk,t,presetn) is begin if(t='0')then enable <= "0111"; seg7 <= " "; elsif(presetn = '0') then count <= "1111"; elsif((clk='1' and clk'event) and (t='1')) then count <= count + 1; a<= count(3); b<= count(2); c<= count(1); d <= count(0); r1 <= (((not b)and (not c) and (not d)) or (a)); r2 <= (((not b)and (not c) and (not d)) or (not a)); g1 <= (((b and (not c)) or ((not b) and d) or (c and (not d))) and (not a)); g2 <= (((b and (not c)) or ((not b) and d) or (c and (not d))) and (a));

6 y1 <= (b and c and d and (not a)); y2 <= (b and c and d and (a)); if ((g1='1' and sensor1='0') or (g2='1' and sensor2='0')) then count(2 downto 0) <= "111"; b<='1'; c<='1'; d<='1'; end if; temp <= b&c&d; case temp is when "000" => seg7 <= " "; when "001" => seg7 <= " "; when "010" => seg7 <= " "; when "011" => seg7 <= " "; when "100" => seg7 <= " "; when "101" => seg7 <= " "; when "110" => seg7 <= " "; when "111" => seg7 <= " "; when others => seg7 <= " "; end case; case temp is when "000" => enable <= "0111"; when "001" => enable <= "1011"; when "010" => enable <= "1101"; when "011" => enable <= "1110"; when "100" => enable <= "0111"; when "101" => enable <= "1011"; when "110" => enable <= "1101";

7 when "111" => enable <= "1110"; when others => enable <= "0111"; end case; end if; end process; end architecture; Simulation Result:

8 RTL Viewer:

9 Technology Map Viewer: