ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700:
|
|
- Allyson Garrison
- 6 years ago
- Views:
Transcription
1 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted SR Latch S R S R SR LATCH WITH NABL: R R' S R t+ t t+ t t t S S' LATCH WITH NABL: This is essentially an SR Latch, where R = not(), S = R' t+ t S' Instructor: aniel Llamocca
2 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 SYNCHRONOUS CIRCUITS: FLIP FLOPS Flip flops are made out of: o A Latch with an enable input. o An dge detector circuit. The figure depicts an SR Latch, where the enable is connected to the output of an dge etector Circuit. The input to the dge etector is a signal called ''. A signal is a square wave with a fied frequency. R T Period Frequency = /T R' SR Flip Flop dge etector S or S' The edge detector circuit generates short-duration pulses during rising (or falling) edges. These pulses act as enable of the Latch. The behavior of the flip flops can be described as that of a Latch that is only enabled during rising (or falling edges). Flip flops classification: o Positive-edge triggered flip flop: The edge detector circuit generates pulses during rising edges. o Negative-edge triggered flip flop: The edge detector circuit generates pulses during falling edges. S S R Positive edge-triggered R Negative edge-triggered SR Flip Flop S R t+ t+ t t S R t+ = SR + t S R = R (S + t S ) = R (S + S )(S + t ) = R S + R t (on the edge) 2 Instructor: aniel Llamocca
3 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 Flip Flop t+ Flip Flop dge etector T Flip Flop t+ = (on the edge) T T T t+ t t t+ = T t (on the edge) JK Flip Flop J K J K J K t+ t t+ = J t + K t (on the edge) t Synchronous/Asynchronous Inputs So far, the flip flops can only change their outputs on the rising (or falling edge). The outputs are usually changed due to a change in the inputs. These inputs are known as synchronous inputs, as the inputs' state is only checked on the rising (or falling) edges. However, in many instances, it is useful to have inputs that force the outputs to a value prn immediately, disregarg the rising (or falling edges). These inputs are known as asynchronous inputs. In the eample, we see a Flip Flop with two asynchronous inputs: o prn: Preset (active low). When prn='', the output q becomes. o : Clear (active low). When ='', the output q becomes. If prn and are both, usually is given priority. A Flip flop could have more than one asynchronous inputs, or none. 3 Instructor: aniel Llamocca
4 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 PRACTIC XRCISS. Complete the timing diagram of the circuit shown below: 2. Complete the VHL description of the circuit shown below: library ieee; use ieee.std_logic_64.all; entity circ is port ( a, b, s,, : in std_logic; q: out std_logic); end circ; architecture a of circ is a b s begin --??? end a; 3. Complete the timing diagram of the circuit shown below. If the frequency of the signal is 25 MH, what is the frequency (in MH) of the signal? '' T 4. Complete the timing diagram of the circuit whose VHL description is shown below: library ieee; use ieee.std_logic_64.all; entity circ is port (,, : in std_logic; q: out std_logic); end circ; architecture a of circ is signal qt: std_logic; begin process (,, ) begin if = then qt <= ; elsif ( event and = ) then if = then qt <= not (qt); end if; end if; end process; q <= qt end a; 4 Instructor: aniel Llamocca
5 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall Complete the timing diagram of the circuit shown below: a b Full Adder s y FA cin cout s a b s 6. Complete the VHL description of the synchronous sequential circuit whose truth table is shown below: library ieee; use ieee.std_logic_64.all; entity circ is port ( A, B, C: in std_logic;, : in std_logic; q: out std_logic); end circ; architecture a of circ is begin --??? end a; X A B t+ C t t X X 7. Complete the timing diagram of the circuit shown below: J K y y 8. Complete the timing diagram of the circuit shown below: Latch L L 5 Instructor: aniel Llamocca
6 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 RGISTRS: N-BIT RGISTR: This is a collection of 'n' -type flip flops, where each flip flop independently stores one bit. The flip flops are connected in parallel. They also share the same and signals. n n n- n-2 n- n-2 N-BIT SHIFT RGISTR: This is a collection of 'n' -type flip flops, connected serially. The flip flops share the same and signals. The serial input is called '', and the serial output is called 'dout'. The flip flop outputs (also called the parallel output) are called = n n 2. epeng on how we label the bits, we can have: Right shift register: The input bit moves from the MSB to the LSB, and Left shift register: The input bit moves from the LSB to the MSB. RIGHT SHIFT RGISTR: dout dout n- n-2 n-3 dout n- n-2 n-3 LFT SHIFT RGISTR: dout dout 2 n- dout 2 n- Timing iagram eample: Instructor: aniel Llamocca
7 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 Parallel access shift register: This is a shift register in which we can write data on the flip flops in parallel. s_l = shifting operation, s_l = parallel load. The figure below shows a 4-bit parallel access shift register s_l 2 s_l Adg enable to flip flops: In many instances, it is very useful to have a signal that controls whether the value of the flip flop is kept. The following circuit represent a flip flop with synchronous enable. When =, the flip flop keeps its value. When =, the flip flop grabs the value at the input. We can thus create n-bit registers and n-bit shift registers with enable. Here, all the flip flops share the same enable input. RGISTR: RIGHT SHIFT RGISTR: LFT SHIFT RGISTR: n n dout dout dout dout n- n-2 n-3 2 n- 7 Instructor: aniel Llamocca
8 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 Parallel access shift register with enable All the flip flops share the same enable input s_l 2 s_l 8 Instructor: aniel Llamocca
9 prn LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 SYNCHRONOUS COUNTRS Counters are useful for: counting the number of occurrences of a certain event, generate time intervals for task control, track elapsed time between two events, etc. Counters are made of flip flops and combinatorial logic. They are usually designed using Finite State Machines (FSM). Synchronous counters change their output on the edge (rising or falling). ach flip flop shares the same input signal. If the initial count is ero, each flip flop shares the input signal. COUNTR CLASSIFICATION: a) Binary counter: An n bit counter counts from to 2 n. The figure depicts a 2-bit counter. b) Modulus counter: A counter modulo N counts from to N-. Special case: BC (or decade) counter: Counts from to 9. 4 BC counter c) Up/down counter: Counts both up and down, under command of a control input. d) Parallel load counter: The count can be given an arbitrary value. e) Counter with enable: If enable =, the count stops. If enable =, the counter counts. This is usually done by connecting the enable inputs of the flip flops to a single enable. f) Ring counter: Also called one-hot counter (only one bit is at a time). It can be constructed using a shift register. The output of the last stage is fed back to the input to the first stage, which creates a ring-like structure. The asynchronous signal startn sets the initial count to (first bit set to ). ample (4-bits):,,,,, The figure below depicts an n bit ring counter. n- n-2 n-3 startn g) Johnson counter: Also called twisted ring counter. It can be constructed using a shift register, where the output of the last flip flop is fed back to the first stage. The result is a counter where only a single bit has a different value for two consecutive counts. All the flip flops share the asynchronous signal, which sets the initial count to. ample (4 bits):,,,,,,,,, The figure below depicts an n bit Johnson counter. n- n-2 n-3 9 Instructor: aniel Llamocca
10 MUX LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 RANOM ACCSS MMORY MULATOR The following sequential circuit represents a memory with 8 addresses, where each address holds a 4-bit data. The memory positions are implemented by 4-bit registers. The reset and signals are shared by all the registers. ata is written or read onto/from one of the registers (selected by the signal address ). Writing onto memory (wr_rd = ): The 4-bit input data (_in) is written into one of the 8 registers. The address signal selects which register is to be written. Here, the 7-segment display must show. For eample: if address =, then _in is written into register 5. Reag from memory (wr_rd = ): The MUX output appears on the 7-segment display (headecimal value). The address signal selects the register from which data is read. For eample: If address =, then data in register 2 must appear on the 7-segment display. If data in register 2 is, then the symbol A appears on the 7-segment display. reset wr_rd _in[3..] 4 2 address[2..] wr_rd 3 ecoder ecoder: HX to 7 segments Instructor: aniel Llamocca
11 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 FINIT STAT MACHINS: Sequential circuits are also called Finite State Machines (FSMs), because the functional behavior of these circuits can be represented using a finite number of states (flip flop outputs). The signal sets the flip flops to an initial state. Classification: - Moore machine: Outputs depend solely on the current state of the flip flops. - Mealy machine: Outputs depend on the current state of the flip flops as well as on the input to the circuit. Only for Mealy Machine Inputs Combinatorial Circuit Flip Flops n (states) Combinatorial Circuit Outputs Any general sequential circuit can be represented by the figure above (Finite State Machine model). A sequential circuit with certain behavior and/or specification can be formally designed using the Finite State Machine method: drawing a State iagram and coming up the citation Table. esigning sequential circuits using Finite State Machines is a powerful method in igital Logic esign. ample: 2-bit gray-code counter with enable and output:,,,,, The output is when the present count is. The count is the same as the states encoded in binary. First step: raw the State iagram and State Table. If we were to implement the state machine in VHL, this is the only step we need. = / / / S S4 / Second step: State Assignment. We assign unique flip flop states to our state labels (S, S2, S3, S4). Notice that this is arbitrary. However, we can save resources if we assign each state to the count that we desire. Then, the output count is just the flip flops outputs. S: = S2: = S3: = S4: = / / S2 / S3 / / PRSNT STAT S S2 S3 S4 S S2 S3 S4 NXT NXT STAT COUNT S S2 S3 S4 S2 S3 S4 S Instructor: aniel Llamocca
12 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 Third step: citation table. Here, we replace the state labels by the flip flop states: PRSNT STAT NXTSTAT (t) (t) (t+) (t+) Fourth step: citation equations and minimiation. (t + ) and (t + ) are the net state of the flip flops, i.e. these signals are to be connected to the inputs of the flip flops. (t+) (t+) (t + ) = + (t + ) = + = Output only depends on the present state. Outputs, are the states and they only depend (in terms of the combinational output circuit) on the present state. Thus, this is a Moore FSM. Fifth step: Circuit implementation. state S S S2 S3 S3 S4 S4 S S2 S2 ample: 2-bit counter with enable and output. The output is when the present count is. The count is the same as the states encoded in binary. First step: raw the State iagram and State Table. If we were to implement the state machine in VHL, this is the only step we need. / PRSNT NXT NXT = / STAT STAT COUNT / / S S4 / / / S2 / S3 / S S2 S3 S4 S S2 S3 S4 S S2 S3 S4 S2 S3 S4 S 2 Instructor: aniel Llamocca
13 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 Second step: State Assignment. We assign unique flip flop states to our state labels (S, S2, S3, S4). Notice that this is arbitrary. However, we can save resources if we assign each state to the count that we desire. Then, the output count is just the flip flops outputs. S: = S2: = S3: = S4: = Third step: citation table. Here, we replace the state labels by the flip flop states: PRSNT STAT NXTSTAT (t) (t) (t+) (t+) Fourth step: citation equations and minimiation. (t + ) and (t + ) are the net state of the flip flops, i.e. these signals are to be connected to the inputs of the flip flops. (t+) (t+) (t + ) = + + (t + ) = + = Output only depends on the present state. Outputs, are the states and they only depend (in terms of the combinational output circuit) on the present state. Thus, this is a Moore FSM. Fifth step: Circuit implementation. state S S S2 S3 S3 S4 S4 S S2 S2 Note: In these 2-bit counters, the states are represented by the outputs of the flip flops:,. They also happen to be the outputs of the FSM. This is common in counters, as the count is usually the same as the flip flop outputs. 3 Instructor: aniel Llamocca
14 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 ample: BC counter. Outputs: (3..),. When the count reaches, becomes. Moore FSM = '' S =,= S2 =,= S3 =2,= S4 =3,= S5 =4,= S =9,= S9 =8,= S8 =7,= S7 =6,= S6 =5,= ample: FSM. Input: w. Output:. This is a Moore FSM as only depends on the present state. = w= w= w= w= w= S = S2 = w= S3 w= S4 w= = = S5 = w= w= w= w= w= w= w= S9 = w= S8 = w= S7 = w= S6 = rstn w state S S S2 S9 S8 S9 S S2 S3 S2 S3 S4 S5 S4 S3 S4 4 Instructor: aniel Llamocca
15 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 ALGORITHMIC STAT MACHIN (ASM) CHARTS: Gray counter, = when = Sequence etector (with overlap) = / / = / / / / S / S2 S / S2 / S3 / / S4 / / S3 / / S6 / / / S5 / / S4 / / S = S = S2 S2 S3 S3 S4 S4 S5 S6 5 Instructor: aniel Llamocca
16 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 XAMPL: ARBITR CIRCUIT Three devices can request access to a certain resource at any time (eample: access to a bus made of tri-state buffers, only one tri-state buffer can be enabled at a time). The FSM can only grant access to one device at a time.there should be a priority level among devices. If the FSM grants access to one device, one must wait until the request signal to that device is deasserted (i.e. set to ero) before granting access to a different device. VIC req priority grant VIC 2 grant2 req2 r r2 r3 FINIT STAT MACHIN g g2 g3 VIC 3 req3 CONTROL CIRCUIT grant3 Algorithmic State Machine (ASM) chart: S = g,g2,g3 r r 2 r 3 S2 S3 S4 g g2 g3 r r 2 r 3 6 Instructor: aniel Llamocca
17 LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Fall 27 Modifying the rate of change of a Finite State Machine: We usually would like to reduce the rate at which FSM transitions occur. A straightforward option is to reduce the frequency of the input. But this is a very complicated problem when a high precision is required. Alternatively, we can reduce the rate at which FSM transitions occur by inclug an enable signal in our FSM: this means inclug an enable to every flip flop in the FSM. For any FSM transition to occur, the enable signal has to be. Then we assert the enable signal only when we need it. The effect is the same as reducing the frequency of the input. The figure below depicts a counter modulo-n (from to N-) connected to a comparator that generates a pulse (output signal ) of one period every time we hit the count N-. The number of bits the counter is given by n = log 2 N. The effect is the same as reducing the frequency of the FSM to f N, where f is the frequency of the. A modulo-n counter is better designed using VHL behavioral description, where the count is increased by every cycle and is generated by comparing the count to N-. A modulo-n counter could be designed by the State Machine method, but this can be very cumbersome if N is a large number. For eample, if N =, we need states. n Inputs FSM Outputs comparator counter to N- =N-? As an eample, we provide the timing diagram of the counter from to N-, when N=. Notice that is only activated when the count reaches. This signal controls the enable of a state machine, so that the FSM transitions only occur every cycles, thereby having the same effect as reducing the frequency by. We can apply the same technique not only to FSMs, but also to any sequential circuit. This way, we can reduce the rate of any sequential circuit (e.g. another counter) by inclug an enable signal of every flip flop in the circuit. 7 Instructor: aniel Llamocca
ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-378:
LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-378: Computer Hardware esign Winter 26 SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted
More informationELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700:
LCTRICAL AN COMPUTR NGINRING PARTMNT, OAKLAN UNIVRSITY C-27: igital Logic esign Winter 28 SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted
More informationELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY ECE-2700:
SYNCHRONOUS SUNTIAL CIRCUITS Notes - Unit 6 ASYNCHRONOUS CIRCUITS: LATCHS SR LATCH: R S R t+ t t+ t S restricted SR Latch S R S R SR LATCH WITH NABL: R R' S R t+ t t+ t t t S S' LATCH WITH NABL: This is
More informationDIGITAL LOGIC WITH VHDL (Fall 2013) Unit 5
IGITAL LOGIC WITH VHL (Fall 2013) Unit 5 SEUENTIAL CIRCUITS Asynchronous sequential circuits: Latches Synchronous circuits: flip flops, counters, registers. COMBINATORIAL CIRCUITS In combinatorial circuits,
More informationTypes of Control. Programmed Non-programmed. Program Counter Hardwired
Lecture #5 In this lecture we will introduce the sequential circuits. We will overview various Latches and Flip Flops (30 min) Give Sequential Circuits design concept Go over several examples as time permits
More informationWritten exam IE1204/5 Digital Design Friday 13/
Written exam IE204/5 Digital Design Friday 3/ 207 08.00-2.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandqvist tel 08-7904487 Teacher: Valhallavägen, Ahmed Hemani 08-7904469
More informationAdder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits. Sequence detector
Lecture 3 Adder Comparator 7 segment display Decoder for 7 segment display D flip flop Analysis of sequential circuits Counter Sequence detector TNGE11 Digitalteknik, Lecture 3 1 Adder TNGE11 Digitalteknik,
More informationUNIVERSITI MALAYSIA PERLIS
UNIVERSITI MALAYSIA PERLIS SCHOOL OF COMPUTER & COMMUNICATIONS ENGINEERING EKT303/4 PRINCIPLES OF COMPUTER ARCHITECTURE LAB 5 : STATE MACHINE DESIGNS IN VHDL LAB 5: Finite State Machine Design OUTCOME:
More informationUNIT II: Clocked Synchronous Sequential Circuits. CpE 411 Advanced Logic Circuits Design 1
UNIT II: Clocked Synchronous Sequential Circuits CpE 411 Advanced Logic Circuits Design 1 Unit Outline Analysis of Sequential Circuits State Tables State Diagrams Flip-flop Excitation Tables Basic Design
More informationUNIT-III ASYNCHRONOUS SEQUENTIAL CIRCUITS TWO MARKS 1. What are secondary variables? -present state variables in asynchronous sequential circuits 2. What are excitation variables? -next state variables
More informationDIGITAL DESIGN WITH SM CHARTS
DIGITAL DESIGN WITH SM CHARTS By: Dr K S Gurumurthy, UVCE, Bangalore e-notes for the lectures VTU EDUSAT Programme Dr. K S Gurumurthy, UVCE, Blore Page 1 19/04/2005 DIGITAL DESIGN WITH SM CHARTS The utility
More informationComputer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University
Computer Architecture: Part II First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Combinational Circuits Flips Flops Flops Sequential Circuits 204231: Computer
More informationModule-20 Shift Registers
1 Module-20 Shift Registers 1. Introduction 2. Types of shift registers 2.1 Serial In Serial Out (SISO) register 2.2 Serial In Parallel Out (SIPO) register 2.3 Parallel In Parallel Out (PIPO) register
More informationChapter 9. sequential logic technologies
Chapter 9. sequential logic technologies In chapter 4, we looked at diverse implementation technologies for combinational logic circuits: random logic, regular logic, programmable logic. Similarly, variations
More informationChapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011
Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7//2 Ver. 72 7//2 Computer Engineering What is a Sequential Circuit? A circuit consists of a combinational logic circuit and internal memory
More informationDELD MODEL ANSWER DEC 2018
2018 DELD MODEL ANSWER DEC 2018 Q 1. a ) How will you implement Full adder using half-adder? Explain the circuit diagram. [6] An adder is a digital logic circuit in electronics that implements addition
More informationNumber system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished
Number system: the system used to count discrete units is called number system Decimal system: the number system that contains 10 distinguished symbols that is 0-9 or digits is called decimal system. As
More informationlogic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs
Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces
More informationICS 151 Final. (Last Name) (First Name)
ICS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 19 pages including this cover and 3 blank pages. 2. Write down your Student-Id
More informationChapter 9. sequential logic technologies
Chapter 9. sequential logic technologies In chapter 4, we looked at diverse implementation technologies for combinational logic circuits: random logic, regular logic, programmable logic. The similar variants
More informationSolutions. ICS 151 Final. Q1 Q2 Q3 Q4 Total Credit Score. Instructions: Student ID. (Last Name) (First Name) Signature
ICS 151 Final Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 19 pages including this cover and 3 blank pages. 2. Write down your Student-Id
More informationPractical Workbook Logic Design & Switching Theory
Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering
More informationModule -18 Flip flops
1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip
More informationRing Counter. 4-bit Ring Counter using D FlipFlop. VHDL Code for 4-bit Ring Counter and Johnson Counter 1. Contents
VHDL Code for 4-bit Ring Counter and Johnson Counter 1 Contents 1 Ring Counter 2 4-bit Ring Counter using D FlipFlop 3 Ring Counter Truth Table 4 VHDL Code for 4 bit Ring Counter 5 VHDL Testbench for 4
More informationCONTENTS Sl. No. Experiment Page No
CONTENTS Sl. No. Experiment Page No 1a Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC. 2a 3a 4a 5a 6a 1b
More informationDIGITAL ELECTRONICS QUESTION BANK
DIGITAL ELECTRONICS QUESTION BANK Section A: 1. Which of the following are analog quantities, and which are digital? (a) Number of atoms in a simple of material (b) Altitude of an aircraft (c) Pressure
More informationChapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/30/2008
Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/3/28 6/3/28 Computer Engineering Basic Element for Sequential CircuitsSR Latch Latch Store one-bit information (two states of and ) Two inputs,
More informationPage 1. Last time we looked at: latches. flip-flop
Last time we looked at: latches flip flops We saw that these devices hold a value depending on their inputs. A data input value is loaded into the register on the rise of the edge. Some circuits have additional
More informationGomoku Player Design
Gomoku Player Design CE126 Advanced Logic Design, winter 2002 University of California, Santa Cruz Max Baker (max@warped.org) Saar Drimer (saardrimer@hotmail.com) 0. Introduction... 3 0.0 The Problem...
More informationEECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics
EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics I. OVERVIEW I.A Combinational vs. Sequential Logic Combinational Logic (everything so far): Outputs depend entirely on
More informationI hope you have completed Part 2 of the Experiment and is ready for Part 3.
I hope you have completed Part 2 of the Experiment and is ready for Part 3. In part 3, you are going to use the FPGA to interface with the external world through a DAC and a ADC on the add-on card. You
More informationLearning Outcomes. Spiral 2 3. DeMorgan Equivalents NEGATIVE (ACTIVE LO) LOGIC. Negative Logic One hot State Assignment System Design Examples
2-3. Learning Outcomes 2-3.2 Spiral 2 3 Negative Logic One hot State Assignment System Design Examples I understand the active low signal convention and how to interface circuits that use both active high
More informationDEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO ECE-238L:
PATMNT OF LCTICAL AN COMPUT NGINING, TH UNIVITY OF NW MXICO C-238L: Computer Logic eign Fll 23 AYNCHONOU UNTIAL CICUIT: Note - Chpter 5 Ltch: t+ t t+ t retricted Ltch Ltch with enle: ' t+ t t+ t t t '
More informationSpec. Instructor: Center
PDHonline Course E379 (5 PDH) Digital Logic Circuits Volume III Spec ial Logic Circuits Instructor: Lee Layton, P.E 2012 PDH Online PDH Center 5272 Meadow Estatess Drive Fairfax, VA 22030-6658 Phone &
More informationLinear & Digital IC Applications (BRIDGE COURSE)
G. PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY Accredited by NAAC with A Grade of UGC, Approved by AICTE, New Delhi Permanently Affiliated to JNTUA, Ananthapuramu (Recognized by UGC under 2(f) and 12(B)
More informationController Implementation--Part I. Cascading Edge-triggered Flip-Flops
Controller Implementation--Part I Alternative controller FSM implementation approaches based on: Classical Moore and Mealy machines Time state: Divide and Counter Jump counters Microprogramming (ROM) based
More informationCHAPTER FIVE - Flip-Flops and Related Devices
CHAPTER FIVE - Flip-Flops and Related Devices 5.1 5.2 Same Q output as 5.1. 5.3 5.4 57 5.5 One possibility: 5.6 The response shown would occur If the NAND latch is not working as a Flip-Flop. A permanent
More informationClock Signal Review Memory Elements
equential ystems eview ombinational etwork Output value only depends on input value equential etwork Output Value depends on input value and present state value equential network must have some way of
More informationLaboratory Manual CS (P) Digital Systems Lab
Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification
More informationFan in: The number of inputs of a logic gate can handle.
Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationA-PDF Split DEMO : Purchase from to remove the watermark 114 FSM
A-PDF Split DEMO : Purchase from www.a-pdf.com to remove the watermark 114 FSM Xilinx specific Xilinx ISE includes a utility program called StateCAD, which allows a user to draw a state diagram in graphical
More information6.111 Lecture # 19. Controlling Position. Some General Features of Servos: Servomechanisms are of this form:
6.111 Lecture # 19 Controlling Position Servomechanisms are of this form: Some General Features of Servos: They are feedback circuits Natural frequencies are 'zeros' of 1+G(s)H(s) System is unstable if
More informationChapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1
Chapter 4: FLIP FLOPS (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT 1 CHAPTER 4 : FLIP FLOPS Programme Learning Outcomes, PLO Upon completion of the programme, graduates
More informationMixed Synchronous/Asynchronous State Memory for Low Power FSM Design
Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design Cao Cao and Bengt Oelmann Department of Information Technology and Media, Mid-Sweden University S-851 70 Sundsvall, Sweden {cao.cao@mh.se}
More informationWinter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28
Subject Code: 17333 Model Answer P a g e 1/28 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model
More informationENGG1015: lab 3. Sequential Logic
ENGG1015: lab 3 Sequential Logic 1 st Semester 2012-13 This lab explores the world of sequential logic design. By the end of this lab, you will have implemented a working prototype of a Ball ounter that
More informationLecture 3: Logic circuit. Combinational circuit and sequential circuit
Lecture 3: Logic circuit Combinational circuit and sequential circuit TRAN THI HONG HONG@IS.NAIST.JP Content Lecture : Computer organization and performance evaluation metrics Lecture 2: Processor architecture
More informationEE 330 Lecture 44. Digital Circuits. Ring Oscillators Sequential Logic Array Logic Memory Arrays. Final: Tuesday May 2 7:30-9:30
EE 330 Lecture 44 igital Circuits Ring Oscillators Sequential Logic Array Logic Memory Arrays Final: Tuesday May 2 7:30-9:30 Review from Last Time ynamic Logic Basic ynamic Logic Gate V F A n PN Any of
More informationEASTERN MEDITERRANEAN UNIVERSITY COMPUTER ENGINEERING DEPARTMENT CMPE224 DIGITAL LOGIC SYSTEMS VHDL EXPERIMENT VII
EASTERN MEDITERRANEAN UNIVERSITY COMPUTER ENGINEERING DEPARTMENT CMPE224 DIGITAL LOGIC SYSTEMS VHDL EXPERIMENT VII TITLE: VHDL IMPLEMENTATION OF ALGORITHMIC STATE MACHINES OBJECTIVES: VHDL implementation
More informationEC O4 403 DIGITAL ELECTRONICS
EC O4 403 DIGITAL ELECTRONICS Asynchronous Sequential Circuits - II 6/3/2010 P. Suresh Nair AMIE, ME(AE), (PhD) AP & Head, ECE Department DEPT. OF ELECTONICS AND COMMUNICATION MEA ENGINEERING COLLEGE Page2
More informationSr. No. Instrument Specifications. TTL (Transistor-Transistor Logic) based on bipolar junction transistors
MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 01 TITLE OF THE EXPERIMENT: Verify four voltage and current parameters for TTL and CMOS (IC
More information1 Q' 3. You are given a sequential circuit that has the following circuit to compute the next state:
UNIVERSITY OF CALIFORNIA Department of Electrical Engineering and Computer Sciences C50 Fall 2001 Prof. Subramanian Homework #3 Due: Friday, September 28, 2001 1. Show how to implement a T flip-flop starting
More informationCS/EE Homework 9 Solutions
S/EE 260 - Homework 9 Solutions ue 4/6/2000 1. onsider the synchronous ripple carry counter on page 5-8 of the notes. Assume that the flip flops have a setup time requirement of 2 ns and that the gates
More informationCOLLEGE OF ENGINEERING, NASIK
Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASIK LAB MANUAL DIGITAL ELECTRONICS LABORATORY Subject Code: 2246 27-8 PUNE VIDYARTHI GRIHA S COLLEGE OF ENGINEERING,NASHIK. INDEX Batch : - Sr.No Title
More informationLecture 20: Several Commercial Counters & Shift Register
EE2: Switching Systems Lecture 2: Several Commercial Counters & Shift Register Prof. YingLi Tian Nov. 27, 27 Department of Electrical Engineering The City College of New York The City University of New
More informationGATE Online Free Material
Subject : Digital ircuits GATE Online Free Material 1. The output, Y, of the circuit shown below is (a) AB (b) AB (c) AB (d) AB 2. The output, Y, of the circuit shown below is (a) 0 (b) 1 (c) B (d) A 3.
More informationLIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM
LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation
More informationFinite State Machines CS 64: Computer Organization and Design Logic Lecture #16
Finite State Machines CS 64: Computer Organization and Design Logic Lecture #16 Ziad Matni Dept. of Computer Science, UCSB Lecture Outline Review of Latches vs. FFs Finite State Machines Moore vs. Mealy
More informationBrought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja.
Brought to you by Priti Srinivas Sajja PS01CMCA02 Course Content Tutorial Practice Material Acknowldgement References Website pritisajja.info Multiplexer Means many into one, also called data selector
More informationDigital Logic Circuits
Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals
More informationLOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1
LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design
More informationFirst Name: Last Name: Lab Cover Page. Teaching Assistant to whom you are submitting
Student Information First Name School of Computer Science Faculty of Engineering and Computer Science Last Name Student ID Number Lab Cover Page Please complete all (empty) fields: Course Name: DIGITAL
More information1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as
BioE 1310 - Review 5 - Digital 1/16/2017 Instructions: On the Answer Sheet, enter your 2-digit ID number (with a leading 0 if needed) in the boxes of the ID section. Fill in the corresponding numbered
More informationJEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer
JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS 6 Credit Hours Prepared by: Dennis Eimer Revised Date: August, 2007 By Dennis Eimer Division of Technology Dr. John Keck, Dean
More informationHigh Speed Binary Counters Based on Wallace Tree Multiplier in VHDL
High Speed Binary Counters Based on Wallace Tree Multiplier in VHDL E.Sangeetha 1 ASP and D.Tharaliga 2 Department of Electronics and Communication Engineering, Tagore College of Engineering and Technology,
More informationCMOS Digital Integrated Circuits Lec 11 Sequential CMOS Logic Circuits
Lec Sequential CMOS Logic Circuits Sequential Logic In Combinational Logic circuit Out Memory Sequential The output is determined by Current inputs Previous inputs Output = f(in, Previous In) The regenerative
More informationECOM 4311 Digital System Design using VHDL. Chapter 9 Sequential Circuit Design: Practice
ECOM 4311 Digital System Design using VHDL Chapter 9 Sequential Circuit Design: Practice Outline 1. Poor design practice and remedy 2. More counters 3. Register as fast temporary storage 4. Pipelined circuit
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/21 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationImplementing Logic with the Embedded Array
Implementing Logic with the Embedded Array in FLEX 10K Devices May 2001, ver. 2.1 Product Information Bulletin 21 Introduction Altera s FLEX 10K devices are the first programmable logic devices (PLDs)
More informationThe counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive
1 The counterpart to a DAC is the ADC, which is generally a more complicated circuit. One of the most popular ADC circuit is the successive approximation converter. 2 3 The idea of sampling is fully covered
More informationUNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018
UNIVERSITY OF BOLTON [EES04] SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002
More informationUnit-6 PROGRAMMABLE INTERRUPT CONTROLLERS 8259A-PROGRAMMABLE INTERRUPT CONTROLLER (PIC) INTRODUCTION
M i c r o p r o c e s s o r s a n d M i c r o c o n t r o l l e r s P a g e 1 PROGRAMMABLE INTERRUPT CONTROLLERS 8259A-PROGRAMMABLE INTERRUPT CONTROLLER (PIC) INTRODUCTION Microcomputer system design requires
More informationPOWER EFFICIENT DESIGN OF COUNTER ON.12 MICRON TECHNOLOGY
Volume-, Issue-, March 2 POWER EFFICIENT DESIGN OF COUNTER ON.2 MICRON TECHNOLOGY Simmy Hirkaney, Sandip Nemade, Vikash Gupta Abstract As chip manufacturing technology is suddenly on the threshold of major
More informationDigital Circuits Laboratory LAB no. 12. REGISTERS
REGISTERS are sequential logic circuits that store and/or shift binary sequences. can be classified in: memory registers (with parallel load) - latch shift registers (with serial load) combined registers
More informationMAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER-16 EXAMINATION Model Answer
Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate
More informationCS302 - Digital Logic Design Glossary By
CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital
More informationa8259 Features General Description Programmable Interrupt Controller
a8259 Programmable Interrupt Controller July 1997, ver. 1 Data Sheet Features Optimized for FLEX and MAX architectures Offers eight levels of individually maskable interrupts Expandable to 64 interrupts
More informationEXPERIMENT #5 COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 La Rosa EXPERIMENT #5 COMINTIONL and SEUENTIL LOGIC CIRCUITS Hardware implementation and software design I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational
More informationSequential Logic Circuits
Exercise 2 Sequential Logic Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of simple sequential logic circuits; - measure the dynamic parameters of
More informationSRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI
SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF
More informationENHANCING SPEED AND REDUCING POWER OF SHIFT AND ADD MULTIPLIER
ENHANCING SPEED AND REDUCING POWER OF SHIFT AND ADD MULTIPLIER 1 ZUBER M. PATEL 1 S V National Institute of Technology, Surat, Gujarat, Inida E-mail: zuber_patel@rediffmail.com Abstract- This paper presents
More informationAnalog to Digital Conversion
Analog to Digital Conversion 02534567998 6 4 2 3 4 5 6 ANALOG to DIGITAL CONVERSION Analog variation (Continuous, smooth variation) Digitized Variation (Discrete set of points) N2 N1 Digitization applied
More informationElectronics. Digital Electronics
Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,
More informationOn Built-In Self-Test for Adders
On Built-In Self-Test for s Mary D. Pulukuri and Charles E. Stroud Dept. of Electrical and Computer Engineering, Auburn University, Alabama Abstract - We evaluate some previously proposed test approaches
More informationMultiplier and Accumulator Using Csla
IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-issn: 2278-2834,p- ISSN: 2278-8735.Volume 10, Issue 1, Ver. 1 (Jan - Feb. 2015), PP 36-44 www.iosrjournals.org Multiplier and Accumulator
More informationCOMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true
More informationLab #10: Finite State Machine Design
Lab #10: Finite State Machine Design Zack Mattis Lab: 3/2/17 Report: 3/14/17 Partner: Brendan Schuster Purpose In this lab, a finite state machine was designed and fully implemented onto a protoboard utilizing
More informationLecture 02: Digital Logic Review
CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:
More informationEITF35: Introduction to Structured VLSI Design
EITF35: Introduction to Structured VLSI Design Part 4.2.1: Learn More Liang Liu liang.liu@eit.lth.se 1 Outline Crossing clock domain Reset, synchronous or asynchronous? 2 Why two DFFs? 3 Crossing clock
More informationIES Digital Mock Test
. The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code
More informationTheory of Logic Circuits. Laboratory manual. Exercise 4
Zakład Mikroinformatyki i Teorii Automatów Cyfrowych Theory of Logic Circuits Laboratory manual Exercise 4 Asynchronous sequential logic circuits 2008 Krzysztof Cyran, Piotr Czekalski (edt.) 1. Introduction
More informationCHAPTER 5 DESIGNS AND ANALYSIS OF SINGLE ELECTRON TECHNOLOGY BASED MEMORY UNITS
208 CHAPTER 5 DESIGNS AND ANALYSIS OF SINGLE ELECTRON TECHNOLOGY BASED MEMORY UNITS 5.1 INTRODUCTION The objective of this chapter is to design and verify the single electron technology based memory circuits
More informationChapter 10 Counter modules
Manual VIPA System 00V Chapter 0 Counter modules Chapter 0 Counter modules Overview This chapter contains information on the interfacing and configuration of the SSI-module FM 0 S. The different operating
More informationTopics. FPGA Design EECE 277. Combinational Logic Blocks. From Last Time. Multiplication. Dr. William H. Robinson February 25, 2005
FPGA Design EECE 277 Combinational Logic Blocks Dr. William H. Robinson Februar5, 25 http://eecs.vanderbilt.edu/courses/eece277/ Topics Computer, compute to the last digit the value o pi. Mr. Spock (Star
More informationCOMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design
PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits
More informationUSB4. Encoder Data Acquisition USB Device Page 1 of 8. Description. Features
USB4 Page 1 of 8 The USB4 is a data acquisition device designed to record data from 4 incremental encoders, 8 digital inputs and 4 analog input channels. In addition, the USB4 provides 8 digital outputs
More informationWe ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits
Basic Timing Issues We ve looked at timing issues in combinational logic Let s now examine timing issues we must deal with in sequential circuits The fundamental timing issues we considered then apply
More informationLogic 0 Logic To provide an output load (or two) 5 Voltage Measurement Point V CC +5 74LS00 GND
Massachusetts Institute of Technology Department of Electrical Engineering and Computer Science 6.111 - Introductory Digital Systems Laboratory Laboratory 1 Logic Analyzers, Digital Oscilloscopes, and
More informationClass Subject Code Subject Prepared By Lesson Plan for Time: Lesson. No 1.CONTENT LIST: Introduction to UnitII 2. SKILLS ADDRESSED: Learning I year, 02 sem CS6201 Digital Principles & System Design S.Seedhanadevi
More information