CSE 260 Digital Computers: Organization and Logical Design. Midterm Solutions

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Mildred Russell
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1 CSE 260 Digital Computers: Organization and Logical Design Midterm Solutions Jon Turner 2/28/ (10 points). The figure below shows a simulation of the washu-1 processor, with some items blanked out. Fill in the blanks below with the correct value from the corresponding labeled blank in the simulation output. The instruction set appears at the bottom of the page. A. 700C B. 7 C. 00BB D E halt 0001 negate 1xxx immediate load 2xxx direct load 3xxx indirect load 4xxx direct store 5xxx indirect store 6xxx 7xxx 8xxx 9xxx axxx dxxx branch branch if zero branch if positive branch if negative add and - 1 -

2 2. (8 points) Draw a transistor-level diagram (using n-fets and p-fets) of a NAND gate with 3 inputs, A, B and C. Suppose all three inputs are high initially and then A goes low, causing the output of the NAND gate to go from low to high. Let t LH be the time for this high to low transition. Now, suppose that input A goes high again, causing the output to go from high to low. Let t HL be the time for this low to high transition. Which is larger, t LH or t HL? Explain why. t HL is larger because for a high to low transition, charge must flow through three on pull-downs in series. For the low to high transition, charge must flow through just one pull-up. The lower resistance of the single pull-up allows for a faster transition. How much larger? Assume that the on-resistance of an n-fet is the same as the onresistance of a p-fet. About three times larger

3 3. (6 points) The circuit shown below is a 4 bit adder, implemented using LUT4s. The outputs (S 3..S 0) = (A 3..A 0) + (B 3..B 0). What are the logic equations implemented by the LUTs for signals S 2 and C 3 (these LUTs are highlighted with a bold outline)? What is the worst-case propagation delay of this circuit, if each LUT has a delay of 1 ns. The logic equations are and. The worst-case propagation delay is 3 ns

4 4. (15 points) The diagram at right shows a combinational circuit with four bit inputs A and B plus a four bit output X. It also has a one bit input, Z in and a one bit output Z out. How many LUT4s are needed to implement this circuit? If we use one LUT each to generate Z 1, Z 2, Z 3, we can implement the 5 outputs with one additional LUT each for a total of 8 LUTs. We actually don t need to generate Z 1, since both X 1 and Z 2 can each be generated with a single LUT without using Z 1 (since they are functions of just Z in, B 0, A 1 and B 1). We also don t need to generate Z 3, since Z 4 and X 3 can be generated with one LUT each from signals B 2, Z 2, A 3 and B 3. So, 6 is enough. Complete the VHDL module shown below so that it implements the circuit shown. entity foo is port ( A,B : in std_logic_vector(3 downto 0); X: out std_logic_vector(3 downto 0); Zin: in std_logic; Zout: out std_logic ); end foo; architecture a1 of foo is signal Z: std_logic_vector(4 downto 0); begin process(a,b,z,zin) begin Z(0) = Zin; for i = 0 to 3 loop if Z(i) = 1 then X(i) <= A(i) or B(i); else X(i) <= A(i) and B(i); Z(i+1) <= Z(i) xor B(i); Zout <= Z(4); end process; end a1; - 4 -

5 5. (20 points) Complete the diagram shown below to show the circuit implemented by the following VHDL specification. entity foo is port( clk: in std_logic; A, B: in std_logic_vector(7 downto 0); X, Y: out std_logic_vector(7 downto 0); end entity; architecture bar of foo is type statetype is (tennis, pingpong, archery) signal state: statetype; signal Z: std_logic_vector(7 downto 0); begin process (clk,a,z) begin if rising_edge(clk) then Z <= B; case state is when tennis => if A > B then X <= B; state <= archery; when pingpong => if B > Z then Z <= A xor B; state <= tennis; when others => X <= A; state <= pingpong; end case; end if Y <= A + Z; end process; end bar; - 5 -

6 6. (20 points). A pulse pair detector is a circuit with a single input D and an output X, which detects closely spaced pairs of pulses. A pulse is a 0, followed by one or more 1s, followed by a 0. A pair of pulses forms a pulse pair if the second pulse ends within 5 clock ticks after the first one ends. The output X should go high for one clock tick at the end of every pulse pair. If a pulse is counted as part of one pulse pair, it is not also be counted as part of a subsequent pulse pair. That is, the circuit does not count overlapping pairs of pulses as separate pulse pairs. So, if the input is , the output is The state diagram shown below is for a state machine that implements a pulse pair detector. It uses a 3 bit counter, t. Complete the state diagram by filling in all the missing transitions and labeling all the transitions with appropriate conditions and actions

7 7. (15 points) The state diagram shown below is for a sequential circuit that counts the number periods where input A is less than or equal to input B for one or more time steps in a row (lerun), and the number of periods when A>B for at least two time steps in a row (gtrun). A and B are four bits each and there is an eight bit output X equal to lerun gtrun. The circuit also has a reset signal which has been omitted from the diagram. When reset is high, the circuit should go to the start state and lerun and gtrun should both be set to 0. Complete the VHDL module outlined on the next page so that it implements the sequential circuit specified by the state diagram. Include code for the reset and output X

8 entity countruns is port ( clk, reset: in std_logic; A,B: in std_logic_vector(3 downto 0); X: out std_logic_vector(7 downto 0)); end countruns; architecture a1 of ballgame is type state_type is (start, le, gt, gt2); signal state: state_type; signal lerun, gtrun: std_logic_vector(7 downto 0); begin process ( clk ) begin if rising_edge(clk) then if reset = '1' then state <= start; lerun <= x 00 ; gtrun <= x 00 ; else case state is when start => if A <= B then state <= le; lerun <= :erun + 1; else state <= gt; when le => if A > B then state <= gt; endif; when gt => if A > B then state <= gt2; gtrun <= gtrun + 1; else state <= le; lerun <= lerun + 1; endif; when gt2 => if A <= B then state <= le; lerun <= lerun + 1; endif; when others => end case; end process; X <= lerun - gtrun; end a1; - 8 -

9 8. (8 points) For the state machine shown below, assume that the flip flop setup time is 2 ns, the hold time is 0.5 ns and the flip flop propagation delay is between 1 and 3 ns. Also, that the clock skew is 0.3 ns. Is this circuit subject to internal hold time violations? Justify your answer. There are no hold time violations because the minimum flip flop propagation delay is larger than the hold time plus the skew. What is the smallest clock period for which the circuit is not subject to setup time violations? Be sure to take into account any modifications from the previous step. The maximum delay for the next state logic is 5 ns. This gives a minimum clock period of =10.3 ns. What is the latest time relative to the clock, when it is safe for input B to change? Input B has a maximum delay path of 5 ns, so it must be stable by 3+2=5 ns before the clock rises. What is the latest time after the clock when output X can be changing? 3+4=7 ns

Ring Counter. 4-bit Ring Counter using D FlipFlop. VHDL Code for 4-bit Ring Counter and Johnson Counter 1. Contents

Ring Counter. 4-bit Ring Counter using D FlipFlop. VHDL Code for 4-bit Ring Counter and Johnson Counter 1. Contents VHDL Code for 4-bit Ring Counter and Johnson Counter 1 Contents 1 Ring Counter 2 4-bit Ring Counter using D FlipFlop 3 Ring Counter Truth Table 4 VHDL Code for 4 bit Ring Counter 5 VHDL Testbench for 4