UNIVERSITI MALAYSIA PERLIS

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1 UNIVERSITI MALAYSIA PERLIS SCHOOL OF COMPUTER & COMMUNICATIONS ENGINEERING EKT303/4 PRINCIPLES OF COMPUTER ARCHITECTURE LAB 5 : STATE MACHINE DESIGNS IN VHDL

2 LAB 5: Finite State Machine Design OUTCOME: 1) Ability to identify the sequential operation techniques 2) Ability to describe the operation of sequential synthesis 3) Ability to demonstrate the use of architecture types 4) Ability to develop a simple VHDL program in Altera Quartus II software INTRODUCTION Finite State Machines (FSMs) represent an important part of design of almost any more complex digital system. There are used to sequence specific operations, control other logic circuits and provide synchronization of different parts of more complex circuit. FSM is a circuit that is designed to sequence through specific patterns of states in a predetermined manner. The basic idea of an FSM is to store a sequence of different unique states and transition between them depending on the values of the inputs and the current state of the machine. A state is represented by a binary value held on a current state register and clock by a free source. There are two types of FSMs as listed below : 1. Moore machine where the output(s) of the system depend from the current state; and 2. Mealy machine where the output(s) of the system depend from the current state and the input(s) of the system The general structure of an FSM can be presented in Figure 5.1 below. ( Mealy Only ) clk Present State Output (Comb Logic) Output(s) Register Input(s) Next State (Comb Logic) Figure 5.1 : FSM building blocks 1

3 To describe an FSM in VHDL, the states must be enumerated and two processes or more must be involved inside the architecture. The most common behavioral statement used for an FSM to represent the states are the if-elsif-else statements inside a Case statement (sequential staements in a sequential staement). The assignment enumeration process for the states into binary values can basically be seen as the following example : Type states is std_logic_vector(1 downto 0); Constant red : states := 00 ; Constant yellow : states := 01 ; Constant green : states := 10 ; Signal present_state, next_state : states; But can replaced with Type states is (red,yellow,green); Signal present_state, next_state : state; An example of a Moore machine is shown in figure 5.2. An example of a Mealy machine is shown in figure 5.3. Write the following VHDL programs in Altera Quartus II and simulate the result and make comparisons. 2

4 -- Figure Example of a simple Moore type FSM LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY moore_fsm IS PORT( Clk,P : IN STD_LOGIC; R : OUT STD_LOGIC); END moore_fsm; ARCHITECTURE beh OF moore_fsm IS SIGNAL State : STD_LOGIC_VECTOR (1 DownTo 0); CONSTANT A: STD_LOGIC_VECTOR (1 DownTo 0) := "00"; CONSTANT B: STD_LOGIC_VECTOR (1 DownTo 0) := "01"; CONSTANT C: STD_LOGIC_VECTOR (1 DownTo 0) := "10"; CONSTANT D: STD_LOGIC_VECTOR (1 DownTo 0) := "11"; PROCESS (Clk) IF Clk'EVENT AND Clk='1' THEN CASE State IS WHEN A => State <= B; ELSE State <= A; WHEN B => State <= C; WHEN C => State <= D; WHEN D=> State <= B; ELSE State <= A; END CASE; END PROCESS; END beh; R <= '1' WHEN State=D ELSE '0'; 3

5 -- Figure Example of a simple Mealy type FSM LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mealy_fsm IS PORT( Clk,P : IN STD_LOGIC; R : OUT STD_LOGIC); END mealy_fsm; ARCHITECTURE beh OF mealy_fsm IS SIGNAL State : STD_LOGIC_VECTOR (1 DownTo 0); CONSTANT A: STD_LOGIC_VECTOR (1 DownTo 0) := "00"; CONSTANT B: STD_LOGIC_VECTOR (1 DownTo 0) := "01"; CONSTANT C: STD_LOGIC_VECTOR (1 DownTo 0) := "10"; PROCESS (Clk, P) IF Clk'EVENT AND Clk='1' THEN CASE State IS WHEN A => State <= B; WHEN B => State <= C; WHEN C => State <= A; END CASE; END PROCESS; END beh; R <= '1' WHEN (State=C AND P='1') ELSE '0'; 4

6 EXERCISE Question 1 A certain control system will assert every time it detects the data value 1 twice in a row from a string of input data. Using the waveform in figure 5.4 below, design the 1. Moore state machine diagram and VHDL coding 2. Mealy state machine diagram and VHDL coding Figure 5.4 : Question 1 waveform parameter Use the given input waveforms to simulate both your state machines and compare. Question 2 A busy street in Kangar will soon be having a pedestrian crossing system to help overcome the crossing problem for pedestrians due to heavy traffic. This pedestrian crossing system will have 2 types of traffic light, one for the vehicles on the road and the other for the pedestrians. A counter will be allocated for the pedestrians to gauge the time given to cross the street. Figure 5.5 below briefly illustrates the system. RED-GREEN traffic light with counter for pedestrian lane. Traffic Light B Yellow push-button for pedestrians who wishes to cross. Traffic Light A RED-YELLOW-GREEN traffic light for vehicle lane. Figure 5.5 : Illustration of a pedestrian crossing system. 5

7 Operation Basically, the pedestrian crossing system will allow vehicles to pass through the street. Now, lets assume the traffic light for the vehicle lane as A-traffic-light, and the pedestrian traffic light as B-traffic-light. Thus, the primary function is to let the cars flow through when there are no people to cross by giving A-traffic-light the GREEN light (AG) while the pedestrian B-traffic-light is RED (BR). The system will change when someone pushes the yellow button and after a clock cycle, will force A-trafficlight to turn YELLOW (AY). The Yellow light will stay for another clock cycle before A-traffic-light goes RED (AR) and B-traffic-light goes GREEN (BG). At the same time, the pedestrian display will begin to display the countdown period to cross. This pedestrian crossing system is controlled by a sequential state mechanism system. Your task is to create a simple controller system that would operate this pedestrian system process. Construct your controller system using the Moore Modelling approach. Possible states required to control the sequence are as follows : State Output condition State Change Condition A traffic light = Green State A B traffic light = Red Change of state depends on Awaiting push button to be pressed before push button. moving to State B State B A traffic light = Yellow B traffic light = Red - State C Continue to State C A traffic light = Red B traffic light = Green Counter is on Awaiting counter to finish before moving to State A. Table 5.1 : State Transition Table Change of state depends on end of count. Important Note 1. Each state change is assumed to have a clock frequency of approximately 1.0Hz. 2. State transition between A B depends on a toggle switch. 3. State transition between B C is only one clock cycle. 4. State transition between C A occur after countdown reaches 0. Assume the countdown is 5 or 7 seconds. Display the countdown on the 7 segment LEDs. Generate and simulate the VHDL codes in Altera Quartus II for the above traffic light exercise. 6

Ring Counter. 4-bit Ring Counter using D FlipFlop. VHDL Code for 4-bit Ring Counter and Johnson Counter 1. Contents

Ring Counter. 4-bit Ring Counter using D FlipFlop. VHDL Code for 4-bit Ring Counter and Johnson Counter 1. Contents VHDL Code for 4-bit Ring Counter and Johnson Counter 1 Contents 1 Ring Counter 2 4-bit Ring Counter using D FlipFlop 3 Ring Counter Truth Table 4 VHDL Code for 4 bit Ring Counter 5 VHDL Testbench for 4