CHAPTER 16 SEQUENTIAL CIRCUIT DESIGN. Click the mouse to move to the next page. Use the ESC key to exit this chapter.

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1 CHPTER 6 SEQUENTIL CIRCUIT DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter.

2 Contents 6. Summary of Design Procedure for Sequential Circuits 6.2 Design ExampleCode Converter 6.3 Design of Iterative Circuits 6.4 Design of Sequential Circuits Using ROMs and PLs 6.5 Sequential Circuit Design Using CPLDs 6.6 Sequential Circuit Design Using FPGs 6.7 Simulation and Testing of Sequential Circuits 6.8 Overview of Computerided Design

3 Objectives. Design a sequential circuit using gates and flipflops. 2. Test your circuit by simulating it and by implementing it in lab. 3. Design a unilateral iterative circuit. Explain the relationship between iterative and sequential circuit, and convert from one to the other. 4. Show how to implement a sequential circuit using a ROM or PL and flipflops. 5. Explain the operation of CPLDs and FPGs and show how they can be used to implement sequential logic.

4 Summary of Design Procedure for Sequential Circuits. Given the problem Statement, determine the relationship between the input and output sequences and derive state table. Construct a State Graph. 2. Reduce the table to a minimum number of states. Eliminate duplicates rows by row matching and then form an implication table. 3. Use Flip/flops for representing states. ssign a unique combination of F/F states corresponds to in each state in reduced table. 4. Form a transition table. 5. Plot nextstate map and input maps for F/F and derive the input F/F equations. 6. Realize the F/F input equations and output equations using available logic 7. Testing your circuit

5 6.2 Design ExampleCode Converter TBLE 6 t t 2 t 3 X INPUT (BCD) t 3 t t t 2 t Z OUTPUT (excess3) BCD code excess 3 code converter

6 6.2 Design ExampleCode Converter TBLE62 State Table for Code Converter TIME INPUT Sequence Received (Least significant Bit First) Present State Next State X = Present Output(Z) X = t reset B C t B D F C E G D H L t 2 E I M F J N G K P H I J t 3 K L M N P

7 6.2 Design ExampleCode Converter TBLE63 Reduced State Table for Code Converter Time Present State Next State X = Present Output(Z) X = t B C t B C D E E E t 2 D E H H H M t 3 H M H I J K L M N P, and E F G

8 6.2 Design ExampleCode Converter Figure 6: State Graph for Code Converter

9 6.2 Design ExampleCode Converter Figure 62: ssignment Map for Flip Flops Q Q2 Q3 Z B C D E H M Q Q 2Q3 X= xxx X= xxx xxx X= x X= x x (b)transition table

10 6.2 Design ExampleCode Converter Figure 63: Karnaugh Maps for Code Converter Design fter the state assignment has been made the transition table is filled in according to the assignment, and the nextstate maps are plotted as shown in Figure 63

11 6.2 Design ExampleCode Converter Figure 64: Code Converter Circuit Figure 64 shows the resulting sequential circuit

12 6.3 Design of Iterative Circuits Sequential Circuit Design Iterative Design Figure 65: Unilateral Iterative Circuit The simplest form of an iterative circuit consists of a linear array of combinational cells with signals between cells traveling in only one direction.

13 6.3 Design of Iterative Circuits Comparator Design using Iterative Circuit Figure 66: Form of Iterative Circuit for Comparing Binary Numbers Figure 66 shows the form of the iterative circuit, although the number of leads between each pair of cells is not yet know.

14 6.3 Design of Iterative Circuits TBLE 64 State Table for Comparator S i S i+ X i Y i = Z Z 2 Z 3 X=Y S S S 2 S S X>Y S S S S S X<Y S 2 S 2 S 2 S 2 S 2

15 6.3 Design of Iterative Circuits TBLE 65 State ssignment and Transition Table for Comparator a i b i x i y i = a i+ b i+ Z Z 2 Z 3 Equations for the first cell (a=b= ) a b 2 2 = = a b + + x x ' y y ' b a ' ' = = x x ' y y '

16 6.3 Design of Iterative Circuits Figure 67:Typical Cell for Comparator

17 6.3 Design of Iterative Circuits Figure 68: Output Circuit for Comparator output maps, equations, and circuit. Z = if X < Y, Z 2 = if X = Y, Z 3 = if X > Y

18 6.3 Design of Iterative Circuits Figure 69: Sequential Comparator for Binary Numbers Figure 69 shows the resulting circuit.

19 6.4 Design of Sequential Circuits Using ROMs and PLs Sequential Circuit can be designed using a ROM and F/F s TBLE 66: Revisit the Code Converter Design (a)state table Present Next State Present Output (Z) State X= X= B C B D E C E E D H H E H M H M

20 6.4 Design of Sequential Circuits Using ROMs and PLs TBLE 66 (b)transition table Q Q2 Q3 Z Q Q 2 Q 3 X= X= X= X= B C D E H K D, Q = Q D2 = Q2 and D3 = 3

21 6.4 Design of Sequential Circuits Using ROMs and PLs TBLE 66 x x x x x x x x x x x x D 3 D 2 D Z Q 3 Q 2 Q X (c)truth table *ROM OUTPUTS (Z,D,D 2 and D 3 ) *ROM INPUTS (X,Q,Q 3 and Q 3 )

22 6.4 Design of Sequential Circuits Using ROMs and PLs Figure 6:Realization of Table 6.6(a) Using a ROM ROM with four input(2 4 words) and four outputs is required, as shown in Figure6

23 6.4 Design of Sequential Circuits Using ROMs and PLs TBLE 67 D 3 D 2 D Z Q3 Q 2 Q X 3 ' 3 ' ' 2 ' ' 3 ' ' 2 XQ Q X Z XQ Q Q Q X Q Q Q Q D Q Q D Q Q D + = + + = = = = = = + + +

24 6.4 Design of Sequential Circuits Using ROMs and PLs Figure 6: Segment of Sequential PL Q + = D = ' BQ ' + ' B Q

25 6.5 Sequential Circuit Design Using CPLDs Figure 62: CoolRunnerII rchitecture(figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, Inc ll rights reserved.) Figure 62 shows the structure of a Xilinx CoolRunner II CPLD, which uses a PL in each function block.

26 6.5 Sequential Circuit Design Using CPLDs Figure 63: CoolRunnerII Macrocell(Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, Inc ll rights reserved.) Figure 63 represents a CoolRunnerII macrocell and the associated ND array.

27 6.5 Sequential Circuit Design Using CPLDs Figure 64: CPLD Implementation of a Mealy Machine Figure 64 shows how a Mealy sequential machine with two input, two outputs, and two flipflops can be implemented by a CPLD

28 6.5 Sequential Circuit Design Using CPLDs Figure 65: CPLD Implementation of a Shift Register Figure 65 shows how the 4bit loadable rightshift register of Figure 2 5 can be implemented using four macrocells of a CPLD

29 6.5 Sequential Circuit Design Using CPLDs Figure 66: CPLD Implementation of a Parallel dder with ccumulator X + i = X i T INPUT is Y i c i T i = X + i X i = Y i C i Figure 66 shows how three bit of the parallel adder with accumulator of Figure 25 can be implemented using a CPLD.

30 6.6 Sequential Circuit Design Using FPGs Figure 67: Xilinx Virtex/Spartan II CLB (Figure based on figures and text owned by Xilinx, Inc., Courtesy of Xilinx, Inc. Xilinx, Inc ll rights reserved.)

31 6.6 Sequential Circuit Design Using FPGs Figure 68: FPG Implementation of a Mealy Machine Figure 68 shows how a Mealy sequential machine with two inputs, two output, and two flipflops can be implemented by a FPG.

32 6.6 Sequential Circuit Design Using FPGs Figure 69: FPG Implementation of a Shift Register *Figure 69 shows how the 4bit loadable rightshift register Figure 25 can be implemented using an FPG. Q D D f 3 f ' = CE Q is the 3 ' = Sh D 3 + CED 3 f = ( Ld + ' Sh)( Sh D D input to flip flop3 + ShSI 3 + ShSI) therefore

33 6.6 Sequential Circuit Design Using FPGs Figure 62: FPG Implementation of a Parallel dder with ccumulator Figure 62 shows how three bits of the parallel adder with accumulator of Figure 25 can be implemented using an FPG

34 6.7 Simulation and Testing of Sequential Circuits Figure 62: Simulator Output for an Inverter Figure 62 shows the output from an inverter which has a nominal delay of ns, a minimum delay of 5 ns, and a maximum delay of 5 ns.

35 6.7 Simulation and Testing of Sequential Circuits Figure 622: Simulation Screen for Figure 37 Figure 622 shows a simulator screen for testing the Mealy sequential circuit of Figure 37.

36 6.7 Simulation and Testing of Sequential Circuits Figure 623 Figure 623 shows the simulator input waveform for the example of Figure 622,using the test sequence X=.

37 6.7 Simulation and Testing of Sequential Circuits Figure 624: Using a Shift Register to Generate Synchronized Inputs The former can be accomplished by loading the inputs into a shift register, and then using the circuit clock to shift them into the circuit one at a time, as shown in figure 624.

38 6.7 Simulation and Testing of Sequential Circuits Figure 625

39 6.7 Simulation and Testing of Sequential Circuits Figure 626: Synchronizer with Two D FlipFlops Figure 626 shows a more reliable synchronizer that uses two D flipflop to synchronize a single asynchronous input,x

40 6.7 Overview of Computerided Design Functions performance of CD tools Generation and Minimization of logic equation Generation of bit patterns for programming PLD s Schematic Capture Simulation Synthesis tools IC design and Layout Test Generation PC board Layout

41 6.7 Simulation and Testing of Sequential Circuits Design a small digital systems with an FPG. Draw a block diagram of the digital system. Define the required control signals and construct state graph and describes the required sequence of operations 2. Workout a detailed logic design using gates, F/F,register, counter,adders, etc (HDL) 3. Construct a logic diagram using a schematic capture program(hdl) 4. Simulate and debug the logic diagram and make any necessary corrections to the design(hdl) 5. Run an implementation program that fits the design into the target FPG 6. Simulation and verifying 7. Download the bit pattern into FPG and test.

EECS 150 Homework 4 Solutions Fall 2008

EECS 150 Homework 4 Solutions Fall 2008 Problem 1: You have a 100 MHz clock, and need to generate 3 separate clocks at different frequencies: 20 MHz, 1kHz, and 1Hz. How many flip flops do you need to implement each clock if you use: a) a ring