Sr. No. Instrument Specifications. TTL (Transistor-Transistor Logic) based on bipolar junction transistors

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1 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 01 TITLE OF THE EXPERIMENT: Verify four voltage and current parameters for TTL and CMOS (IC 74LSXX, 74HCXX). AIM : To Verify voltage and current parameters for TTL and CMOS (IC 74LSXX, 74HCXX). APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: LOGIC FAMILIES: Three major logic families: TTL (Transistor-Transistor Logic) based on bipolar junction transistors CMOS (Complementary Metal Oxide Semiconductor) based on MOSFETs ECL (Emitter-Coupled Logic), based on bipolar junction transistors Originally, TTL chips were fast but used lots of power, and CMOS chips used little power but were slow. CMOS chips are sensitive to static discharge, and must be handled carefully. Subfamilies within the TTL Family Description Designator Example Standard TTL None

2 Low-Power Schottky LS 74LS04 Advanced Low-Power Schottky ALS 74ALS04 Fast F 74F04 Some Subfamilies within the CMOS Family Description Designator Example Standard CMOS 4069 Pin-compatible with 7400 series C 74C04 High-Speed CMOS HC 74HC04 Advanced High-Speed CMOS AHC 74AHC04 Low-Voltage CMOS (3.3 V) LVC 74LVC04 Advanced Low-Voltage CMOS (2.5 V) ALVC 74ALVC04 DC Supply Voltages: TTL chips are optimized for 5 V supply, and cannot tolerate voltages far above or below 5 V. CMOS chips may be optimized for 5 V, 3.3 V, 2.5 V, or 1.8 V supplies. Most CMOS chips can tolerate a much wider range of supply voltages than TTL chips Fan-out Fan-out means the number of load inputs that a given output can drive. 2

3 Input and Output Currents Four key current parameters: IIH = the current flowing through an input pin when it s HIGH. IIL = the current flowing through an input pin when it s LOW. IOH = the current flowing through an output pin when it s HIGH. IOL = the current flowing through an output pin when it s LOW. Logic Levels Four key voltage parameters when you re interfacing logic: VIH(min) = the minimum voltage that an input pin will recognize as a HIGH. VIL(max) = the maximum voltage an input pin will recognize as a LOW. VOH(min) = the minimum voltage that can appear on a HIGH output pin. VOL(max) = the maximum voltage that can appear on a LOW output pin. Logic levels for TTL 3

4 Noise Margin The noise margin is the room for error between the voltage that an output pin produces and the voltage that an input pin expects. VNH = VOH(min) VIH(min) VNL = VIL(max) VOL(max) Different logic families have different voltage and current specifications. These differences can cause problems when you connect a gate from one family to a gate from another family. Interfacing Example: TTL to CMOS A TTL HIGH output may be as low as 2.4 V. But a CMOS input expects HIGHs to be at least 3.33 V. Solution: use a pull-up resistor, as shown in Figure. 4

5 Interfacing Example: CMOS to TTL A CMOS LOW output can only sink 0.51 ma. But a TTL LOW input may source as much as 1.6 ma. OBSERVATION TABLE: Parameter 74LSXX 74HCXX VIH VIL VOH VOL IIH IIL IOH IOL 5

6 DIAGRAM: CONCLUSION: 6

7 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 02 TITLE OF THE EXPERIMENT: Study of IC-74LS153 as a Multiplexer. AIM : A) Design and Implement 8:1 MUX using IC-74LS153 & Verify its Truth Table B) Design & Implement any given 4 variable function using IC74LS153. Verify its Truth Table. APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: MULTIPLEXER: A multiplexer is a circuit with many inputs but only one output.the selection of particular input line is controlled by a set of selection lines. Normally there are n input lines and m select lines whose bit combination determines which input is selected. It s a special combinational circuit that is one of the most widely used standard circuits in digital design. The multiplexer (or data selector) is a logic circuit that gates one out of several inputs to a single output. The output selected is controlled by a set of select inputs. For selecting one out of n inputs for connection to the output, a set of m select inputs is required, where 2 m = n. Depending upon the digital code applied at the select inputs one out of n data sources is selected and transmitted to a single output channel. Normally, a strobe (or enable) input (G) is incorporated which helps in cascading and it is generally active-low, which means it performs its intended operation when it s LOW TYPES OF MUTIPLEXER 2:1 MUX 4:1 MUX 8:1 MUX 16:1 MUX 7

8 DIFFERENT MULTIPLEXER IC s IC no. Description Output Quad 2:1 MUX Same as input Quad 2:1 MUX Inverted input Dual 4:1 MUX Same as input 74151A 8:1 MUX Complementary outputs :1 MUX Inverted inputs :1 MUX Inverted input TRUTH TABLE FOR 8:1 MULTIPLEXER USING IC 74153: E S 1 S 0 I 0 I 1 I 2 I 3 I 4 I 5 I 6 I 7 Z X X X X X X X X X X X X X X X 0 X X X X X X X 1 X X X X X X X X 0 X X X X X X X 1 X X X X X X X X 0 X X X X X X X 1 X X X X X X X X 0 X X X X X X X 1 X X X X X X X X 0 X X X X X X X 1 X X X X X X X X 0 X X X X X X X 1 X X X X X X X X X X X X X X X 1 1 8

9 Internal Logic Diagram for IC 74LS153 DUAL 4:1 MUX 9

10 COMBINATIONAL CIRCUITS (1) f (A,B,C) = E A B C Y Design: Logic Diagram: 10

11 (2) f (A,B,C,D) = A B C D Y Design: Logic Diagram: 11

12 (3) FULL ADDER A B C SUM(S) CARRY Design: Logic Diagram: 12

13 ADVANTAGES OF MUX 2. It reduces number of wires. 3. It reduces the circuit complexity and cost. 4. We can implement any combinational circuits. 5. It simplifies the logic design 6. It doesn t need the k maps and simplification APPLICATIONS OF MULTIPLEXER 1. Used as a data selector to select one out of many data inputs. 2. Used for simplification of logic design. 3. In data acquisition system 4. In designing the combinational circuits. 5. In D/A converters. CONCLUSION: 13

14 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 03 TITLE OF THE EXPERIMENT: Study of IC as Demultiplexer/Decoder. AIM : : A) Design and implementation full adder and full subtractor function using IC B) Design and implementation 3-bit code converter using IC-74138(Gray to Binary/Binary to Gray). APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: DEMULTIPLEXER: A demultiplexer is a circuit that receives information on a single line and transmits information on one of the possible output lines. The selection of specific output line is controlled by the values of n selection lines. It has only one input, n outputs and m select inputs. It performs converse operation as that of a multiplexer. It receives one input and distributes it over several outputs. At a time only one output line is selected by the select lines and the input is transmitted to the selected output line. There is also an enable input which is responsible for enabling the demultiplexer. 14

15 INPUT D Y0 Y1 Y2 OUTPUTS ENABLE E Yn S1 S2 Sm Relation between m select lines and n outputs is: N=2 m SR.NO IC NUMBER FUNCTION Dual 1:4 DEMUX Dual 1:4 DEMUX :8 DEMUX :8 DEMUX :16 DEMUX :16 DEMUX IC DEMULTIPLEXER: This is 1:8 demultiplexer IC. Also it is a 3:8 decoder. It has 3 enable pins out of which 1 is active high and 2 are active low. The active low enable pin can be used as data line IC DEMULTIPLEXER: It is a dual 1:4 demultiplexer IC. Also it is 2:4 decoder. The active low enable pin can be used as data line. 15

16 TRUTH TABLE FOR IC 74138: E3 E1 E2 A2 A1 A0 O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7 X X H X X X H H H H H H H H X H X X X X H H H H H H H H L X X X X X H H H H H H H H H L L L L L L H H H H H H H H L L L L H H L H H H H H H H L L L H L H H L H H H H H H L L L H H H H H L H H H H H L L H L L H H H H L H H H H L L H L H H H H H H L H H H L L H H L H H H H H H L H H L L H H H H H H H H H H L 16

17 IMPELEMENT FULL ADDER AND SUBTRACTOR USING IC74138: 1) FULL ADDER: TRUTH TABLE: A B C SUM CARRY Logic Diagram: 17

18 2)FULL SUBTRACTOR: TRUTH TABLE: A B C DIFFERENCE BORROW Logic Diagram: 18

19 3) Gray to Binary code converter Binary Input Gray Output B2 B1 B1 G2 G1 G0 Logic Diagram: 19

20 4) Binary to Gray code converter Gray Input Binary Output G2 G1 G0 B2 B1 B1 Logic Diagram: CONCLUSION: 20

21 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 04 TITLE OF THE EXPERIMENT: Study of IC-74LS83 as a BCD adder. AIM : a) Design and implement 1 digit BCD adder using IC 7483 b) Design and implement 4-bit Binary subtractor using IC 7483 APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: BCD Adder BCD adder is a circuit that adds 2 BCD digits and produces a sum in BCD form. BCD addition procedures can be summarized as follows, 1. Add 2 BCD number using binary addition. 2. If the 4-bit sum is greater than 9 or if carry is generated, the sum is invalid. To correct the sum, add 0110 to sum, if carry is generated from this addition, add it to the next higher order BCD digit. 3. If the 4-bit sum is less than 9 or equal to 9, the sum is in proper BCD form Thus, to implement, BCD adder we require, a. A 4-bit binary adder for initial addition. b. Logic circuitry to detect sums greater than 9. c. Another 4-bit adder to add 0110 in the sum if the sum is greater than 9 or if carry is generated. The logic circuit to determine sum greater than 9 can be determined by Boolean expression of the given truth table: - simplifying the 21

22 TRUTH TABLE:-detection of invalid BCD: Cout S3 S2 S1 S0 Y

23 KARNAUGH MAP :- Cout = 0 Cout = 1 As shown in figure the BCD number are first added in the top 4-bit binary adder to produce a binary sum. When sum is less than equal to 9 and Cout =0 zero is added to the binary sum. When a sum greater than 9 or Cout=1 binary 0110 is added to the binary sum. The output carry generated from the bottom binary adder can be ignored, since it supplies information already available at the output carry terminal. 23

24 CIRCUIT DIAGRAM: 24

25 4-BIT BINARY SUBTRACTOR: The problem of subtraction can be converted into that of addition if 1 s and 2 s complement representation are used for representing negative numbers. The two numbers A and B can be of same sign or of opposite sign. If the two numbers are of unlike sign, the problem of overflow or underflow occurred. PROCEDURE: 1. Find 1 s complement of subtrahend. 2. Add it with minuend along with carry in equal to 1 using binary adder IC. 3. Check the output of adder, if carry is generated then ignore the carry and subtraction output is positive which is available at sum output. Sign of answer is represented by MSB of sum. If MSB is 0 then output is positive and if MSB is 1 then output is negative. 4. If carry is not generated then subtraction output is negative and it is in 2 s complement form, which is available at sum output. 5. If output is in 2 s complement form, then find the magnitude of subtraction result by taking 2 s complement of answer. CIRCUIT DIAGRAM: 25

26 CONCLUSION: 26

27 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 05 TITLE OF THE EXPERIMENT: Study of IC 74LS85 as a Magnitude Comparator. AIM : A) Design and Implement 4 bit comparator. B) Design and Implement 8 bit comparator. APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: COMPARATOR: Digital Comparator is a combinational logic device which compares two n bit binary input words. It has 3 outputs namely A>B, A=B and A<B. Depending upon the result of comparison, one of these outputs will be high. TYPES OF COMPARATOR 1 Bit Comparator 2 Bit Comparator 4 Bit Comparator up to n Bit Comparator For comparison of binary numbers having more bits, cascading of ICs can be done. But the IC generally used in the market is IC 74LS85 (4 Bit comparator) 27

28 DIFFERENT COMPARATOR IC s IC no. Description Output 74LS85 4 Bit Magnitude Comparator A>B / A=B / A<B 74HC/HCT688 8 Bit Identity Comparator Only for A=B SN54ALS688 8 Bit Identity Comparator Only for A=B EXAMPLE 1 BIT COMPARATOR A B A>B A=B A<B In above truth table, 2 bits A and B are compared. Explanation- Case 1: A=0, B=0 and A=1, B=1 A=B is High. Case 2: A=1, B=0 A>B is High. Case 3: A=0, B=1 A<B is High. 28

29 TRUTH TABLE FOR 4 BIT COMPARATOR USING IC 74LS85-: Comparing Inputs Cascading Inputs Outputs A>B A=B A<B A>B A=B A<B A>B X X X A<B X X X A=B X 1 X A=B 1 X X A=B X X Logic Diagram: 29

30 4 BIT COMPARATOR USING IC 74LS85 Comparing Inputs Cascading Inputs Outputs A>B A=B A<B A>B A=B A<B 8 BIT COMPARATOR Outputs of first IC are connected to Cascading inputs of next IC. LSBs are given as input to the first IC and next four MSB bits to the next IC. Logic Diagram: 30

31 Compare any two 8 bit numbers and write the result - Number 1 (8 Bit) Number 2 (8 Bit) Binary Decimal Value Binary Decimal Value A>B A=B A<B ADVANTAGES OF COMPARATOR 1. Easy designing of Circuit. 7. For decision making in electronic circuits, comparators are helpful. APPLICATIONS OF COMPARATOR 6. Comparators are used in Microprocessors and Microcontrollers. 7. Comparators are used in Arithmetical and Logic Unit. CONCLUSION: 31

32 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 06 TITLE OF THE EXPERIMENT: Study of counter IC. AIM : 1) Design & Implement MOD N & MOD- MN using IC 74LS90 and draw Timing diagram. 2) Design & Implement MOD N & MOD- MN using IC 74LS93 and draw Timing diagram. APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: A) BASIC INTERNAL STRUCTURE OF IC 7490 IC 7490 is a TTL MSI decade counter. It contains four master slave flip-flops and additional gating to provide a divide-by-two counter and a three stage binary counter which provides a divide by 5 counter. (MOD-5) IC 7490 is a MOD-10 or decade counter. It can be used for designing 32

33 symmetrical Bi-quinary divide by 10 counter. In this application clock is applied to input B and QD output is connected to input A. the output is obtained at QA output. It is a perfect square wave at a frequency equal to fclk/10. PIN NAME AND DESCRIPTION PIN NAME DESCRIPTION 1 Input B Clock input to internal MODS ripple counter 2 Ro(1), Ro(2) Gates, zero reset input. These are active low. When both are zero all output are zero. 3 VCC +5V DC 4 RQ(1), RQ(2) These are gate set with nine output. 5 QD, QC, QB Output of internal MOD counter. 6 GND Logic GND acts as reference. 7 QA Output of internal MOD-2 counter. 8 Input A Clock input to flip flop A which is negative edge triggered. PINDIAGRAM : 33

34 IC 7490 AS DECADE COUNTER TRUTH TABLE FOR IC 7490 CLOCK QD QC QB QA CIRCUIT DIAGRAM: Decade Counter using T FF 34

35 TIMING DIAGRAM: IC 7490 AS MOD-6 COUNTER TRUTH TABLE OF MOD-6 COUNTER: CLOCK QA QB QC QD CIRCUIT DIAGRAM: 35

36 IC 7490 AS MOD-100 COUNTER CIRCUIT DIAGRAM: 36

37 B) IC 74 LS93 4-Bit Ripple Counter : The output Q0 must be externally connected to input CP1. The input count pulses are applied to input CP0. Simultaneous divisions of 2, 4, 8, and 16 are performed at the Q0, Q1, Q2, and Q3 outputs as shown in the truth table. 3-Bit Ripple Counter The input count pulses are applied to input CP1. Simultaneous frequency divisions of 2, 4, and 8 are available at the Q1, Q2, and Q3 outputs. Independent use of the first flip-flop is available if the reset function coincides with reset of the 3-bit ripplethrough counter. IC 7493 AS MOD-12 COUNTER CIRCUIT DIAGRAM: TIMING DIAGRAM: 37

38 IC 7493 AS MOD-86 COUNTER CIRCUIT DIAGRAM: CONCLUSION: 38

39 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 07 TITLE OF THE EXPERIMENT: Study of Synchronous counter. AIM : Design & Implement Up/Down counter & MOD N Up/Down counter using IC 74HC191 and draw Timing diagram. APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: SYNCHRONOUS COUNTER IC 74191:- IC is a 16 pin IC that is synchronous, 4-bit binary, up/down reversible counter. Synchronous operation is obtained by having all the flip-flops clocked simultaneously so that the outputs change simultaneously. This method eliminates the output counting spikes normally associated with an asynchronous (ripple) counter. INPUTS: 1) Clock input: The clock of this IC is a positive edge triggered. 2) Enable: The IC gets activated when this pin is connected to ground. 3) Up/Down: This input determines the direction of count. When low, the IC counts up and when high the IC counts down. 4) Load: The outputs of the IC may be preset to any level by placing low on the input load and entering the data. The output will change independent of the level of the clock input. 5) Data inputs A, B, C, and D: These are used to preset a particular data in the IC. 6) OUTPUTS QA, QB, QC, and QD: They are the outputs of the master slave JK flip-flops. 39

40 7) Max/Min: This is the special output IC. When the count is in up mode and reaches 15 i.e. 1111, which is over flow condition, then output of Max/Min goes high. When in down count mode and 0000 is present at output it is underflow condition and again the output goes high. Ripple clock: This is also special output of the IC. Just like Max/Min, output of ripple clock goes low for overflow and under flow conditions. But the only difference is that this output is low for only the negative clock cycles and not for entire clock cycles (normally high). PIN CONFIGURATION OF IC 74191: PIN DESCRIPTION PIN NUMBER DESCRIPTION Data input (PO to P3) Parallel load PL 4 data inputs lines with P0 LSB and P3 as MSB Data present on input lines appears as output when P =0 Count enable input CE It enables counting when CE =0 4 output with Q0 as LSB and Q3 as MSB Output (Q0 to Q3) If this input is low, up counting takes place UP/down and if high, down counting takes place. Clock input (CP) This is clock input for clock 40

41 Terminal counter (TC) Ripple clock (RC) As the counter reaches max (15) or min (0), it is indicated by a `high pulse` on TC output. This is an active low output. It is normally high. As the counter reaches max (15) or min (0), it is indicated by a `high pulse` on ripple clock. It is used for cascading. TRUTH TABLE: Operating Mode Inputs Output PL U/D CE CP P0 to P3 Parallel Load L X X X L L MOD-10 UP COUNTER FROM 6 TO 15 USING IC TRUTH TABLE: Decimal Binary L X X X H H Count Up H L L Î X Count Up Count Down H H L Î X Count Down Hold(no change) H X H X X No Change 41

42 Initially 0110 is given to data inputs DCBA. To count from 6 onwards, load is initially connected to ground and then to VCC. Pin 5 is grounded for up counting. IC uses positive edge triggered clock and hence for every clock pulse it starts incrementing output i.e. 6,7,8,9 After 15,output tries to go to 0 and so OR gates are connected at output pins and output of OR gate is connected to load pin. Hence output of OR gate is 0 and hence load is activated and it loads at output pins. BLOCK DIAGRAM OF MOD-10 UP COUNTER FROM 6 TO 15 USING IC : MOD-8 UP COUNTER FROM4 TO 11 USING IC KARNAUGH MAP: 42

43 BLOCK DIAGRAM OF MOD-8 UP COUNTER FROM 4TO 11 USING IC : TIMING DIAGRAM: CONCLUSION: 43

44 MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 08 TITLE OF THE EXPERIMENT: Study of Shift Register AIM : 1) Design & Implement pulse train generator using Shift register IC -74HC194/IC- 74LS95(Use right shift/left shift) 2) Design & Implement 4 bit ring Counter/Twisted ring counter using Shift register IC- 74HC194/IC-74LS95. APPARATUS: Sr. No. Instrument Specifications 1 Digital Trainer Kit 2 IC s used THEORY: There are couples of ways to define a Register used in Digital Electronics. Registers are data storage devices that are more sophisticated than latches. A register is a group of binary cells suitable for holding binary information. A group of cascaded flip flops used to store related bits of information is known as a register. Application of Registers These are used in computers for Temporary storage Data transferring Data manipulation As counters Shift Register A register that is used to assemble and store information arriving from a serial source is called a shift register. Each flip flop output of a shift register is a connected to the input of the following flip flop and a common clock pulse is applied to all flip flops, clocking them synchronously. Hence the shift register is a synchronous sequential circuit. An n-bit 44

45 shift register consists of n Flip Flops and the gates control the shift operation. There are four types of Shift Registers: 1. Serial-In, Serial-Out (SISO) 2. Parallel-In, Serial-Out (PISO) 3. Serial-In, Parallel-Out (SIPO) 4. Parallel-In, Parallel-Out (PIPO) In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, which has the output of anyone but the last flip-flop connected to the "data" input of the next one in the chain, resulting in a circuit that shifts by one position the one-dimensional "bit array" stored in it, shifting in the data present at its input and shifting out the last bit in the array, when enabled to do so by a transition of the clock input. More generally, a shift register may be multidimensional; such that its "data in" input and stage outputs are themselves bit arrays: this is implemented simply by running several shift registers of the same bit-length in parallel. Shift registers can have both parallel and serial inputs and outputs. These are often configured as serial-in, parallel-out (SIPO) or as parallel-in, serial-out (PISO). There are also types that have both serial and parallel input and types with serial and parallel output. There are also bi-directional shift registers which allow shifting in both directions: L R or R L. The serial input and last output of a shift register can also be connected together to create a circular shift register. SERIAL-IN, SERIAL-OUT: These are the simplest kind of shift registers. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the first flip-flop's output. The bit on the far right (i.e. 'Data Out') is shifted out and lost. The data are stored after each flip-flop on the 'Q' output, so there are four storage 'slots' available in this arrangement; hence it is a 4-Bit Register. To give an idea of the shifting pattern, imagine that the register holds 0000 (so all storage slots are empty). As 'Data In' presents 1,0,1,1,0,0,0,0 (in that order, with a pulse at 'Data Advance' each time. This is called clocking or strobing) to the register, this is the result. The left hand column corresponds to the left-most flip-flop's output pin, and so on. So the serial output of the entire register is As you can see if we were to continue to input data, we would get exactly what was put in, but offset by four 'Data Advance' cycles. This 45

46 arrangement is the hardware equivalent of a queue. Also, at any time, the whole register can be set to zero by bringing the reset (R) pins high. This arrangement performs destructive readout - each datum is lost once it been shifted out of the right-most bit. SERIAL-IN, PARALLEL-OUT: Data is input serially, as described in the SISO section above. Once the data has been input, it may be either read off at each output simultaneously, or it can be shifted out and replaced. PROCEDURE: I) Symmetrical Schmitt trigger i) Make connections as shown in the circuit diagram ii) Apply +VCC and VEE as +/-12V respectively. iii) Apply sine wave input with 10 V p-p, with freq = 1KHz iv) Observe the waveforms on Dual mode of the CRO and verify the UTP and LTP are according to the design and sketch the same. Observe the Hysteresis by keeping the CRO in X-Y mode & sketch the same. 46

47 PARALLEL IN SERIAL OUTPUT: PARALLEL IN PARALLEL OUT: IC 74194: 47

48 TRUTH TABLE: Operating MR S1 S0 DSR DSL Pn Q0 Q1 Q2 Q3 Mode Reset L L L L L Hold H L L Q0 Q1 Q2 Q3 Shift Left H H L L Q1 Q2 Q3 L H H L H Q1 Q2 Q3 H Shift Right H L H L L Q0 Q1 Q2 H L H H H Q0 Q1 Q2 Parallel Load H H H Pn P0 P1 P2 P3 A)IMPLEMENT ATION OF PULSE TRAIN: THEORY: A sequence generator is the Sequential circuit, which generates a prescribed sequence as its output. The output sequence is in synchronization with the clock input. It is possible to design a sequence generator using shift register. The output of an n-bit shift register is applied at inputs to combinational circuit called next next state Decoder. The output of the next state decoder is applied as inputs of shift register the combinational circuit IDs designed as per the requirement of sequence. The Given Sequence is TRUTH TABLE: Q3 Q2 Q1 Q0 D I/P 48

49 K-map: Logic Diagram: 49

50 B)4 BIT RING COUNTER/TWISTED RING COUNTER IC -74HC194/IC- 74LS95. The synchronous Ring Counter example above, is preset so that exactly one data bit in the register is set to logic 1 with all the other bits reset to 0. To achieve this, a CLEAR signal is firstly applied to all the flip-flops together in order to RESET their outputs to a logic 0 level and then a PRESET pulse is applied to the input of the first flip-flop ( FFA ) before the clock pulses are applied. This then places a single logic 1 value into the circuit of the ring counter. So on each successive clock pulse, the counter circulates the same data bit between the four flipflops over and over again around the ring every fourth clock cycle. But in order to cycle the data correctly around the counter we must first load the counter with a suitable data pattern as all logic 0 s 50

51 The MODULO or MODULUS of a counter is the number of states the counter counts or sequences through before repeating itself and a ring counter can be made to output any modulo number. A mod-n ring counter will require n number of flip-flops connected together to circulate a single data bit providing n different output states. Johnson Ring Counter: The Johnson Ring Counter or Twisted Ring Counters, is another shift register with feedback exactly the same as the standard Ring Counter above, except that this time the inverted output Q of the last flip-flop is now connected back to the input D of the first flip-flop as shown below. The main advantage of this type of ring counter is that it only needs half the number of flip-flops compared to the standard ring counter then its modulo number is halved. So a n-stage Johnson counter will circulate a single data bit giving sequence of 2n different states and can therefore be considered as a mod-2n counter. This inversion of Q before it is fed back to input D causes the counter to count in a different way. Instead of counting through a fixed set of patterns like the normal ring counter such as for a 4-bit counter, 0001 (1), 0010 (2), 0100 (4), 1000 (8) and repeat, the Johnson counter counts up and then down as the initial logic 1 passes through it to the right replacing the preceding logic 0. A 4-bit Johnson ring counter passes blocks of four logic 0 and then four logic 1 thereby producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit pattern continually repeats. For example, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000 and this is demonstrated in the following table below. 51

52 Clock Pulse No FFA FFB FFC FFD Logic Diagram of Ring Counter: 52

53 Logic Diagram of Twisted Ring Counter: CONCLUSION: 53