PROPOSED SCHEME OF COURSE WORK

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1 PROPOSED SCHEME OF COURSE WORK Course Details: Course Title : Digital System Design Course Code :15EC1110 L T P C : Program: : B.Tech. Specialization: : Electrical and Electronics Engineering Semester : V Prerequisites : Digital Logic Design. Courses to which it is a prerequisite : - Course Outcomes (COs): At the end of the course the student will be able to 1 Design digital Systems by ASM Charts. 2 Design Sequential Circuits using different Methods. 3 Illustrate Various Fault Models. 4 Generate Test Vectors by various Test Generation Methods. 5 Describe Fault Diagnosis in Sequential Circuits. Program Outcomes (POs): A graduate of Electrical and Electronics Engineering will be able to Apply the knowledge of basic sciences and electrical and electronics engineering fundamentals to solve 1 the problems of power systems and drives Analyze power systems that efficiently generate, transmit and distribute electrical power in the context of present Information and Communications Technology. Design and develop electrical machines and associated controls with due considerations to societal and environmental issues. Design and conduct experiments, analyze and interpret experimental data for performance analysis. Apply appropriate simulation tools for modeling and evaluation of electrical systems. Apply the electrical engineering knowledge to assess the health and safety issues and their consequences. Demonstrate electrical engineering principles for creating solutions for sustainable development. Develop a techno ethical personality that help to serve the people in general and Electrical and Electronics Engineering in particular. 9 Develop leadership skills and work effectively in a team to achieve project objectives. 10 Communicate effectively in both verbal and written form

2 11 Understand the principles of management and finance to manage project in multi disciplinary environments. 12 Pursue life-long learning as a means of enhancing the knowledge and skills. Course Outcome Vs Program Outcomes: COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 CO-1 M S S CO-2 M S S CO-3 M S CO-4 M S M S CO-5 M S M S S - Strongly correlated, M - Moderately correlated, Blank - No correlation Assessment Methods: / Quiz / Seminar / Mid-Test / End Exam Teaching-Learning and Evaluation W ee k TOPIC / CONTENTS 1 Unit I Design of Digital Systems: ASM charts Course Outcom es Sample questions Q1.Explain about each block used in ASM Chart. Q2.Mention Rules for Drawing an ASM Chart TEACHING - LEARNING STRATEGY Assessment Method 2 ASM charts, ASM Chart for Binary Multiplier 3 ASM Chart for Dice Game, Reduction of state tables 4 Reduction of state tables, state s Q1.Draw the ASM Chart for D Flip-Flop Q2.Draw the Block Diagram for Binary Multiplier and explain its operation and plot the ASM Chart for it. Q1.Draw the Block Diagram for Dice Game and explain its operation and plot the ASM Chart for it. Q2.What are the advantages of Reduced State Table. Q1 Reduce the following state table to a minimum number of states using Implication chart Method shown in Table-1

3 5 state s UNIT II Sequential Circuit Design: design of Iterative circuits Table-1 Q2.Describe the rules for state assignment. Q1. Find a good state assignment for the following State Table using the three guidelines (do not Reduce the table first.) Try to satisfy as many of the adjacency conditions as possible shown in Table-2 6 design of sequential circuits using ROMs and PLAs Introduction to CPLD, sequential circuit design using CPLD 7 sequential circuit design using CPLD Introduction to FPGA sequential circuit design using FPGAs Table-2 Q2.Design a Sequential Comparator for Binary Numbers with State Table and derive the necessary Boolean Expressions Q1.Explain about Cool Runner-II Macro cell Q2.Implement a Shift Register using CPLD Q1.Explain about Spartan-II CLB Block Q2.Implement a Half Adder using FPGA 8 sequential circuit design using FPGAs 9 MID TEST-1, 10 UNIT III Fault Modeling: Q1.Implement a Mealy Machine using FPGA Q2.Implement a Parallel Adder with Accumulator using FPGA Q1.What are the implications of Stuck at Faults on the Digital

4 Need for testing Fault classes and models Stuck at faults 11 Bridging faults, transition and intermittent faults. Introduction to DFT 12 Introduction to DFT, Random testing,direct Testing, PRBS Generator for 4 Bit system design? Explain With examples. Q2.Explain about various Fault Classes Q1.Explain about Bridging Faults Q2.Explain about Level Sensitive Scan Based Design Q1.Design a PRBS Generator for 4 Bit and explain how random Sequences are generated? Q2.Explain about Parallel Scan II II II 13 UNIT-IV Test Pattern Generation: Path Sensitization technique, Boolean difference method 14 Boolean difference method, Kohavi algorithm CO4 CO4 Q1.With an example, explain the procedure involved in the path sensitization technique. Q2. Explain the Boolean difference method with an Q1.Find the test vectors of all SA0 and SA1 faults of the circuit function F=x1x2+x1x3 x4 +x2x4 using Kohavi algorithm Q2. A circuit realizes the function z=x1 x4+x2 x3+x1x4. Using Boolean Difference method, find the test vectors SA0 II II 15 D algorithm 16 UNIT V Test Pattern Generation: PODEM, transition count testing, Signature analysis and testing for bridging faults 17 Fault Diagnosis In Sequential Circuits: State identification and fault detection experiment, Machine identification, Design of fault detection experiment. 18 MID TEST 2, Faults and SA1 Faults on line X1 Q1.Explain the procedure involved in D- Algorithm with an Q2.What do you mean by Singular Cover, Propagation D Cube Q1.With an example, explain the transition count testing method and also mention advantages and disadvantages of this method. Q2. Explain the operation of Signature Analysis Q1. Explain the procedure of designing a fault detection experiment with the help of an Q2.What are the advantages of Distinguishing Sequence II II II

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PROPOSED SCHEME OF COURSE WORK

PROPOSED SCHEME OF COURSE WORK Course Details: Course Title : LINEAR AND DIGITAL IC APPLICATIONS Course Code : 13EC1146 L T P C : 4 0 0 3 Program: : B.Tech. Specialization: : Electrical and Electronics