Testing Digital Systems I
|
|
- Blake Murphy
- 5 years ago
- Views:
Transcription
1 Testing igital Systems I Testing igital Systems I Lecture 8: Boolean Testing Using Fault Models ( Algorithm) Instructor: M. Tahoori Copyright 2, M. Tahoori TS I: Lecture 8 Specific-Fault Oriented Test Generation Three Approaches Internal Line Values Assigned ( Algorithm) (Roth-966) -cubes Bridging faults Logic gate function change faults Input Values Assigned (POEM) (Goel 98) X-Path-Check Path propagation constraints to limit ATPG search space Backtracing Input and Internal Values Assigned (FAN) (Fujiwara) Efficiently constrained backtarce Copyright 2, M. Tahoori TS I: Lecture 8 2 Lecture 8
2 Testing igital Systems I Fault Cone Fault Cone and -frontier Set of hardware affected by fault -frontier Set of gates closest to POs with fault effect(s) at input(s) -frontier Fault Cone Copyright 2, M. Tahoori TS I: Lecture 8 3 Algorithm Copyright 2, M. Tahoori TS I: Lecture 8 4 Lecture 8 2
3 Testing igital Systems I -Algorithm -- Roth IBM (966) Fundamental concepts invented: First complete ATPG algorithm -Cube -Calculus Implications forward and backward Implication stack Backtrack Test Search Space Copyright 2, M. Tahoori TS I: Lecture 8 5 Algorithm Assigning internal line values : Test for Stuck-at- on Lower Input to Gate B Activate Fault Put on Faulty Lead Copyright 2, M. Tahoori TS I: Lecture 8 6 Lecture 8 3
4 Testing igital Systems I Algorithm Test for Stuck-at- on Lower Input to Gate B Implication Record Effects of Previous Assignments Copyright 2, M. Tahoori TS I: Lecture 8 7 Algorithm Propagation Select Path to Propagate to Output Single versus Multiple Path Propagation Copyright 2, M. Tahoori TS I: Lecture 8 8 Lecture 8 4
5 Testing igital Systems I Algorithm Propagation Assign Required Gate Input Values s on other inputs of OR, NOR Gates with or Input s on other inputs of AN, NAN Gates with or Input Copyright 2, M. Tahoori TS I: Lecture 8 9 Line Justification Find Input Assignment to Place Value v on Line g Path Tracing Approach Propagate Signals using Element Functions Must Choose Element Input Values and Paths Primitive cube of an element (gate) with output Z List of prime implicants of Z and Z' AN A B Z NAN A B Z Implication (no choices) ecision (choices) Copyright 2, M. Tahoori TS I: Lecture 8 Lecture 8 5
6 Testing igital Systems I Algorithm Line Justification Assign Required Gate Input Values on lower input of C to give on output Copyright 2, M. Tahoori TS I: Lecture 8 Implication Algorithm Record Effects of Previous Assignments Test is U,V,Y,Z =,,,d IFFICULTY Internal Line Values May be Inconsistent Copyright 2, M. Tahoori TS I: Lecture 8 2 Lecture 8 6
7 Testing igital Systems I Algorithm Test for Stuck-at- on Gate A Output Activate Fault Put on Faulty Lead Copyright 2, M. Tahoori TS I: Lecture 8 3 Algorithm Test for Stuck-at- on Gate A Output Implication Record Effects of Previous Assignments Copyright 2, M. Tahoori TS I: Lecture 8 4 Lecture 8 7
8 Testing igital Systems I Algorithm Test for Stuck-at- on Gate A Output Propagation Select Path to Propagate to Output Copyright 2, M. Tahoori TS I: Lecture 8 5 Algorithm Propagation Assign Required Gate Input Values s on other inputs of OR, NOR Gates with or Input s on other inputs of AN, NAN Gates with or Input Copyright 2, M. Tahoori TS I: Lecture 8 6 Lecture 8 8
9 Testing igital Systems I Algorithm Test for Stuck-at- on Gate A Output Implication Record Effects of Previous Assignments Copyright 2, M. Tahoori TS I: Lecture 8 7 Algorithm Test for Stuck-at- on Gate A Output Propagation Select Alternate Path to Propagate to Output Copyright 2, M. Tahoori TS I: Lecture 8 8 Lecture 8 9
10 Testing igital Systems I Algorithm Test for Stuck-at- on Gate A Output Implication Record Effects of Previous Assignments Test is U,V,Y,Z =,,, Copyright 2, M. Tahoori TS I: Lecture 8 9 Calculus Copyright 2, M. Tahoori TS I: Lecture 8 2 Lecture 8
11 Testing igital Systems I Singular Cover Singular Cover Minimal set of input signal assignments to show essential prime implicants of Karnaugh map Gate AN 2 3 Inputs A B X X Output d Gate NOR 2 3 Inputs d e X X Output F Copyright 2, M. Tahoori TS I: Lecture 8 2 Algorithm -Cube A collapsed truth table entry AN gate Rows & 3 Reverse inputs And two cubes Interchange and A B d Copyright 2, M. Tahoori TS I: Lecture 8 22 Lecture 8
12 Testing igital Systems I Algorithm Intersection efines how different -cubes can coexist for different gates in logic circuit If one cube assigns a specific signal value, the other cubes must assign either that same value or X = X = X = = X = X = X X = X, represent incompatible assignments, represent incompatibility if both present X X X Copyright 2, M. Tahoori TS I: Lecture 8 23 Algorithm Primitive -cube of Failure (PF) Models fault including SA: represented by SA: represented by : AN gate PF for output SA is PFs for output SA are X, X Propagation -cube Models conditions under which fault effect propagates through gate Copyright 2, M. Tahoori TS I: Lecture 8 24 Lecture 8 2
13 Testing igital Systems I Implication Procedure. Model fault with appropriate PF 2. Select propagation -cubes to propagate fault effect to a PO (-drive procedure) 3. Select singular cover cubes to justify internal circuit signals (Consistency procedure) Algorithm s main problem Selects cubes and singular covers arbitrarily Copyright 2, M. Tahoori TS I: Lecture 8 25 Algorithm Copyright 2, M. Tahoori TS I: Lecture 8 26 Lecture 8 3
Testing Digital Systems II
Lecture : Introduction Instructor: M. Tahoori Copyright 206, M. Tahoori TDS II: Lecture Today s Lecture Logistics Course Outline Review from TDS I Copyright 206, M. Tahoori TDS II: Lecture 2 Lecture Logistics
More informationDesign a pattern generator with low switching activity to test complex combinational logic with high test coverage
Design a pattern generator with low switching activity to test complex combinational logic with high test coverage 1 Jay B Dabhi 1 VLSI & Embedded Systems Design GTU PG School, Ahmedabad, India E Mail:
More informationFault Diagnosis in Combinational Logic Circuits: A Survey
IJSRD - International Journal for Scientific Research & Development Vol. 3, Issue 02, 2015 ISSN (online): 2321-0613 Fault Diagnosis in Combinational Logic Circuits: A Survey Sarang S. Samangadkar 1 Shridhar
More informationTesting Digital Systems II. Problem: Fault Diagnosis
Testing Digital Systems II Lecture : Logic Diagnosis Instructor: M. Tahoori Copyright 26, M. Tahoori TDSII: Lecture Problem: Fault Diagnosis test patterns Circuit Under Diagnosis (CUD) expected response
More informationOverview ECE 553: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES. Motivation. Modeling Levels. Hierarchical Model: A Full-Adder 9/6/2002
Overview ECE 3: TESTING AND TESTABLE DESIGN OF DIGITAL SYSTES Logic and Fault Modeling Motivation Logic Modeling Model types Models at different levels of abstractions Models and definitions Fault Modeling
More information: Principles of Automated Reasoning and Decision Making Midterm
16.410-13: Principles of Automated Reasoning and Decision Making Midterm October 20 th, 2003 Name E-mail Note: Budget your time wisely. Some parts of this quiz could take you much longer than others. Move
More informationPROPOSED SCHEME OF COURSE WORK
PROPOSED SCHEME OF COURSE WORK Course Details: Course Title : Digital System Design Course Code :15EC1110 L T P C : 4 0 0 3 Program: : B.Tech. Specialization: : Electrical and Electronics Engineering Semester
More informationOdd-Prime Number Detector The table of minterms is represented. Table 13.1
Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1
More informationTest Automation - Automatic Test Generation Technology and Its Applications
Test Automation - Automatic Test Generation Technology and Its Applications 1. Introduction Kwang-Ting (Tim) Cheng and Angela Krstic Department of Electrical and Computer Engineering University of California
More informationECE 301 Digital Electronics
ECE 301 Digital Electronics Constraints in Logic Circuit Design (Lecture #14) The slides included herein were taken from the materials accompanying Fundamentals of Logic Design, 6 th Edition, by Roth and
More informationAn Efficient Automatic Test Pattern Generator for
VLSI Design 1994, Vol. 2, No. 3, pp. 199-207 Reprints available directly from the publisher Photocopying permitted by license only (C) 1994 Gordon and Breach Science Publishers S.A. Printed in the United
More informationCourse Outline Cover Page
College of Micronesia FSM P.O. Box 159 Kolonia, Pohnpei Course Outline Cover Page Digital Electronics I VEE 135 Course Title Department and Number Course Description: This course provides the students
More informationEECS-140/141 Introduction to Digital Logic Design Lecture 4:Simplification in Logic Synthesis
EECS-140/141 Introduction to Digital Logic Design Lecture 4:Simplification in Logic Synthesis I. REVIEW AND INTRODUCTION I.A General Synthesis Procedure I.A.1 Express Function as: I.A.1.a Define variables
More informationDesign for Testability & Design for Debug
EE-382M VLSI II Design for Testability & Design for Debug Bob Molyneaux Mark McDermott Anil Sabbavarapu EE 382M Class Notes Foil # 1 The University of Texas at Austin Agenda Why test? Scan: What is it?
More informationCombinational Logic Design CH002
Combinational Logic Design CH002 Figure 2.1 Circuit as a black box with inputs, outputs, and specifications Figure 2.2 Elements and nodes Figure 2.3 Combinational logic circuit Figure 2.4 Two OR implementations
More informationAsst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02)
2145230 Aircraft Electricity and Electronics Asst. Prof. Thavatchai Tayjasanant, PhD Email: taytaycu@gmail.com aycu@g a co Power System Research Lab 12 th Floor, Building 4 Tel: (02) 218-6527 1 Chapter
More informationSYNTHESIS OF COMBINATIONAL CIRCUITS
HPTER 6 SYNTHESIS O OMINTIONL IRUITS 6.1 Introduction oolean functions can be expressed in the forms of sum-of-products and productof-sums. These expressions can also be minimized using algebraic manipulations
More informationCMSC 2833 Lecture 26. Step Expression Justification
omputer Organiation I. Karnaugh Maps and Minimiation MS Lecture Minimiation with Theorems onsider the Boolean function: FF(xx, yy, ) = xxʹyyʹ + xyʹʹ + xyʹ + xxxxʹ + xxxxxx Step Expression Justification.
More informationEncoders. Lecture 23 5
-A decoder with enable input can function as a demultiplexer a circuit that receives information from a single line and directs it to one of 2 n possible output lines. The selection of a specific output
More informationLecture 15 Analysis of Combinational Circuits
Lecture 15 Analysis of Combinational Circuits Designing Combinational Logic Circuits A logic circuit having 3 inputs, A, B, C will have its output HIGH only when a majority of the inputs are HIGH. Step
More informationChapter 4 Combinational Logic Circuits
Chapter 4 Combinational Logic Circuits Chapter 4 Objectives Selected areas covered in this chapter: Converting logic expressions to sum-of-products expressions. Boolean algebra and the Karnaugh map as
More informationSOPRANO: AN EFFICIENT AUTOMATIC TEST PATTERN GENERATOR FOR STUCK-OPEN FAULTS IN CMOS COMBINATIONAL CIRCUITS
SOPRANO: AN EFFICIENT AUTOMATIC TEST PATTERN GENERATOR FOR STUCK-OPEN FAULTS IN CMOS COMBINATIONAL CIRCUITS Hyung Ki Lee and Dong Sam Ha Department of Eiectrical Engineering Virginia Polytechnic Institute
More informationThis Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations.
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 5 Lecture Title:
More informationChapter 4 Combinational Logic Circuits
Chapter 4 Combinational Logic Circuits Chapter 4 Objectives Selected areas covered in this chapter: Converting logic expressions to sum-of-products expressions. Boolean algebra and the Karnaugh map as
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/21 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev B 4/21/2010 (2:04 PM) Prof. Ali M. Niknejad University of California,
More informationIn this experiment you will study the characteristics of a CMOS NAND gate.
Introduction Be sure to print a copy of Experiment #12 and bring it with you to lab. There will not be any experiment copies available in the lab. Also bring graph paper (cm cm is best). Purpose In this
More informationChapter 1 Introduction to VLSI Testing
Chapter 1 Introduction to VLSI Testing 2 Goal of this Lecture l Understand the process of testing l Familiar with terms used in testing l View testing as a problem of economics 3 Introduction to IC Testing
More informationIDDQ and Diagnosis. Outline. I DDQ and Diagnosis. Introduction. Definition of Diagnosis. Why Diagnosis? Test and Diagnosis Flow
Center for RC eliable omputing I and Diagnosis Stanford University ugust 16, 1999 Outline Introduction oolean Diagnosis ridging Fault Diagnosis Problems I Diagnosis Future Research Topics Summary 1 2 Introduction
More informationBy: Dr. Ahmed ElShafee
Lecture (03) COMBINATIONAL CIRCUIT DESIGN AND SIMULATION USING GATES By: Dr. Ahmed ElShafee ١ Dr. Ahmed ElShafee, ACU : Spring 2018, CSE303 Logic design II Design of Circuits with Limited Gate Fan In In
More informationVLSI Design Verification and Test Delay Faults II CMPE 646
Path Counting The number of paths can be an exponential function of the # of gates. Parallel multipliers are notorious for having huge numbers of paths. It is possible to efficiently count paths in spite
More informationDr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006
COE/EE2DI4 Midterm Test #1 Fall 2006 Page 1 Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006 Instructions: This examination paper includes 10 pages and 20 multiple-choice questions starting
More informationResistive Bridge Fault Modeling, Simulation and Test Generation 1
Resistive Bridge Fault Modeling, Simulation and Test Generation Vijay R. Sar-Dessai Intel orporation, FM5-64 900 rairie ity Road Folsom A 95630 Tel: (96) 356-759 Fax: (96) (96) 377-300 Email: vijay.sar-dessai@intel.com
More informationFebruary IEEE, VI:20{32, 1985.
Acknowledgements The authors thank Joel Ferguson, J. Alicia Grice, Alvin Jee, Haluk Konuk, Rich McGowen, and Carl Roth for technical contributions. This work was supported by the Semiconductor Research
More informationTHE technology independent multilevel logic minimization
1494 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 15, NO. 12, DECEMBER 1996 Perturb and Simplify: Multilevel Boolean Network Optimizer Shih-Chieh Chang, Malgorzata
More information(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification
More informationSOPRANO: AN EFFICIENT AUTOMATIC TEST PATTERN GENERATOR
SOPRANO: AN EFFICIENT AUTOMATIC TEST PATTERN GENERATOR FOR STUCK-OPEN FAULTS IN CMOS COMBINATIONAL CIRCUITS Hyung Ki Lee and Dong Sam Ha De part m e nt of E I ect r i ca I En g i nee r i n g Virginia Polytechnic
More informationDigital Systems Design
Digital Systems Design Digital Systems Design and Test Dr. D. J. Jackson Lecture 1-1 Introduction Traditional digital design Manual process of designing and capturing circuits Schematic entry System-level
More informationDIGITAL ELECTRONICS. Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3
DIGITAL ELECTRONICS Marking scheme : Methods & diagrams : 1 Graph plotting : - Tables & analysis : - Questions & discussion : 6 Performance : 3 Aim: This experiment will investigate the function of the
More informationBCD Adder. Lecture 21 1
BCD Adder -BCD adder A 4-bit binary adder that is capable of adding two 4-bit words having a BCD (binary-coded decimal) format. The result of the addition is a BCD-format 4-bit output word, representing
More informationIntroduction to CMOS VLSI Design (E158) Lecture 5: Logic
Harris Introduction to CMOS VLSI Design (E158) Lecture 5: Logic David Harris Harvey Mudd College David_Harris@hmc.edu Based on EE271 developed by Mark Horowitz, Stanford University MAH E158 Lecture 5 1
More informationLSN 3 Logic Gates. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 3 Logic Gates Department of Engineering Technology LSN 3 Inverter One input and one output Produces a compliment of the input Negation indicator Truth table Active low output In Out 0 1 1 0 Active
More informationIndex. Cadden, W. J., 128 Caelingeart, P., 55, 57 Caldwell. S. H Absorption laws, 20, 29 Adjacency. diagram, 182. SIVE -NOR expressions, 53
Index Absorption laws, 20, 29 Adjacency column, 292 diagram, 182 map, 186, 293 output, 292 row, 292 Adjacent term, 81 Adjustable logic network, 65 Akers, S. B., Jr., 57 Algebraic determination of minimal
More informationAdvanced Digital Design
Advanced Digital Design The Need for a Design Style by A. Steininger Vienna University of Technology Outline Skew versus consistency The need for a design style Hazards, Glitches & Runts Lecture "Advanced
More informationEE 280 Introduction to Digital Logic Design
EE 280 Introduction to Digital Logic Design Lecture 1. Introduction EE280 Lecture 1 1-1 Instructors: EE 280 Introduction to Digital Logic Design Dr. Lukasz Kurgan (section A1) office: ECERF 6 th floor,
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Exam 1 Logistics
Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 1 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and
More informationB.C.A 2017 DIGITAL ELECTRONICS BCA104T MODULE SPECIFICATION SHEET. Course Outline
Course Outline B.C.A 2017 DIGITAL ELECTRONICS BCA104T MODULE SPECIFICATION SHEET The purpose of the course is to teach principles of digital electronics. This course covers varieties of topics including
More informationSynthesis of Combinational Logic
Synthesis of ombinational Logic 6.4 Gates F = xor Handouts: Lecture Slides, PS3, Lab2 6.4 - Spring 2 2/2/ L5 Logic Synthesis Review: K-map Minimization ) opy truth table into K-Map 2) Identify subcubes,
More informationEEE 301 Digital Electronics
EEE 301 Digital Electronics Lecture 1 Course Contents Introduction to number systems and codes. Analysis and synthesis of digital logic circuits: Basic logic functions, Boolean algebra,combinational logic
More informationDIGITAL LOGIC CIRCUITS
LOGIC APPLICATIONS DIGITAL LOGIC CIRCUITS Noticed an analogy between the operations of switching devices, such as telephone switching circuits, and the operations of logical connectives What happens when
More informationScan Side Channel Analysis: a New Way for Non-Invasive Reverse Engineering of a VLSI Device
Scan Side Channel Analysis: a New Way for Non-Invasive Reverse Engineering of a VLSI Device Leonid Azriel Technion Israel Institute of Technology May 6, 2015 May 6, 2015 1 Side Channel Attacks Side Channel
More informationChapter 3 Describing Logic Circuits Dr. Xu
Chapter 3 Describing Logic Circuits Dr. Xu Chapter 3 Objectives Selected areas covered in this chapter: Operation of truth tables for AND, NAND, OR, and NOR gates, and the NOT (INVERTER) circuit. Boolean
More informationLecture 7: Digital Logic
Lecture 7: Digital Logic Last time we introduced the concept of digital electronics i.e., one identifies a range of voltages with the value, and another range with the value But we didn t specify these
More information14:332:231 DIGITAL LOGIC DESIGN. Gate Delays
4:332:23 DIGITAL LOGIC DESIGN Ivan Marsic, Rutgers University Electrical & Computer Engineering all 23 Lecture #8: Timing Hazards Gate Delays hen the input to a logic gate is changed, the output will not
More informationisudoku Computing Solutions to Sudoku Puzzles w/ 3 Algorithms by: Gavin Hillebrand Jamie Sparrow Jonathon Makepeace Matthew Harris
isudoku Computing Solutions to Sudoku Puzzles w/ 3 Algorithms by: Gavin Hillebrand Jamie Sparrow Jonathon Makepeace Matthew Harris What is Sudoku? A logic-based puzzle game Heavily based in combinatorics
More informationVLSI Testing. Yield Analysis & Fault Modeling. Virendra Singh Indian Institute of Science Bangalore
VLSI Testing Yield Analysis & Fault Modeling Virendra Singh Indian Institute of Science Bangalore virendra@computer.org E0 286: Test & Verification of SoC Design Lecture - 2 VLSI Chip Yield A manufacturing
More informationThe prime factorization of 150 is 5 x 3 x 2 x 5. This can be written in any order.
Outcome 1 Number Sense Worksheet CO1A Students will demonstrate understanding of factors of whole numbers by determining the prime factors, greatest common factor, least common multiple, square root and
More informationLogic Circuit Design
Logic Circuit Design we have studied Truth Tables Logic gates Logic algebra K-maps 1 All these are tools Tools Truth Tables Logic gates Logic algebra K-maps 2 All these are tools Tools Truth Tables Logic
More informationEE 42/100 Lecture 24: Latches and Flip Flops. Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad
A. M. Niknejad University of California, Berkeley EE 100 / 42 Lecture 24 p. 1/15 EE 42/100 Lecture 24: Latches and Flip Flops ELECTRONICS Rev A 4/14/2010 (8:30 PM) Prof. Ali M. Niknejad University of California,
More informationEE241 - Spring 2000 Advanced Digital Integrated Circuits. Project Presentations
EE241 - Spring 2000 Advanced Digital Integrated Circuits Lecture 28 Memory Project Presentations 293 Cory Tuesday, May 2, 2-4pm o Murmann, Baytekin o Borinski, Dogan, Markow o Smilkstein, Wong o Zanella,
More information(a) (b) (c) (d) (e) (a) (b) (c) (d) (e)
Exercises 97 Exercises Exercise 2. Write a oolean equation in sum-of-products canonical form for each of the truth tables in Figure 2.8. (d) (e) C C C D Figure 2.8 Truth tables for Exercises 2. and 2.3
More informationAnalysis procedure. To obtain the output Boolean functions from a logic diagram, proceed as follows:
Combinational Logic Logic circuits for digital systems may be combinational or sequential. combinational circuit consists of input variables, logic gates, and output variables. 1 nalysis procedure To obtain
More informationCombinational Logic. Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations
Combinational Logic Combinational Logic Design Process, Three State Buffers, Decoders, Multiplexers, Encoders, Demultiplexers, Other Considerations Copyright (c) 2012 Sean Key Combinational Logic Design
More informationEMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 4: Combinational Logic Circuits. Name: Date:
EXPERIMENT # 4: Combinational Logic Circuits Name: Date: Equipment/Parts Needed: 5V DC Power Supply Digital Trainer (Logic Probe) Breadboard DIP Switch 7400 NAND gate 7402 NOR gate 7404 Inverter 7408 AND
More informationTestability Synthesis for Jumping Carry Adders
VLSI Design, 2002 Vol. 14 (2), pp. 155 169 Testability Synthesis for Jumping Carry Adders CHIEN-IN HENRY CHEN a, * and MAHESH WAGH b a Department of Electrical Engineering, Wright State University, Dayton,
More informationDigital Circuits Introduction
Lecture #6 OUTLINE Logic inary representations Combinatorial logic circuits Chap 7-7.5 Reading EE4 Summer 25: Lecture 6 Instructor: Octavian lorescu Digital Circuits Introduction nalog: signal amplitude
More informationEECS 427 Lecture 21: Design for Test (DFT) Reminders
EECS 427 Lecture 21: Design for Test (DFT) Readings: Insert H.3, CBF Ch 25 EECS 427 F09 Lecture 21 1 Reminders One more deadline Finish your project by Dec. 14 Schematic, layout, simulations, and final
More informationFault Tolerance in VLSI Systems
Fault Tolerance in VLSI Systems Overview Opportunities presented by VLSI Problems presented by VLSI Redundancy techniques in VLSI design environment Duplication with complementary logic Self-checking logic
More informationAdverserial Search Chapter 5 minmax algorithm alpha-beta pruning TDDC17. Problems. Why Board Games?
TDDC17 Seminar 4 Adversarial Search Constraint Satisfaction Problems Adverserial Search Chapter 5 minmax algorithm alpha-beta pruning 1 Why Board Games? 2 Problems Board games are one of the oldest branches
More informationCS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam
CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page
More informationDIGITAL DESIGN WITH SM CHARTS
DIGITAL DESIGN WITH SM CHARTS By: Dr K S Gurumurthy, UVCE, Bangalore e-notes for the lectures VTU EDUSAT Programme Dr. K S Gurumurthy, UVCE, Blore Page 1 19/04/2005 DIGITAL DESIGN WITH SM CHARTS The utility
More informationFunction Table of an Odd-Parity Generator Circuit
Implementation of an Odd-Parity Generator Circuit The first step in implementing any circuit is to represent its operation in terms of a Truth or Function table. The function table for an 8-bit data as
More informationComparative analysis of self checking and monotonic logic Techniques for combinational circuit testing
C o m p a r a t i v e a n a l y s i s o f s e l f c h e c k i n g a n d m o n o t o n i c l o g i c T e c h n i q u e s... Comparative analysis of self checking and monotonic logic Techniques for combinational
More informationIN THIS PAPER, we present a technique focusing on the
102 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 1, JANUARY 2004 Fast Postplacement Optimization Using Functional Symmetries Chih-Wei (Jim) Chang, Ming-Fu
More informationUC Berkeley CS61C : Machine Structures
CS61C L22 Representations of Combinatorial Logic Circuits (1) inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 22 Representations of Combinatorial Logic Circuits 27-3-9 TA David
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC
More informationSubtraction Fact Four-in-a-Row Games
Subtraction Fact Four-in-a-Row Games Thank you for respecting my Terms of Use. You are welcome to You may not More legal stuff The Measured Mom www.themeasuredmom.com My blog has hundreds of free resources
More informationPractical Fault Coverage of Supply Current Tests for Bipolar ICs
Practical Coverage Supply Current Tests for Bipolar ICs Isao Tsukimoto, Masaki Hashizume, Hiroyuki Yotsuyanagi, Takeomi Tamesada Dept. Electronic Engineering, Takuma National College Technology tukimoto@de.takuma-ct.ac.jp
More informationSubject: Analog and Digital Electronics Code:15CS32
Subject: Analog and Digital Electronics Code:15CS32 Syllabus: The Basic Gates : Review of Basic Logic gates, Positive and Negative Logic, Introduction to HDL. Combinational Logic Circuits:Sum-of-Products
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 7 & 8 NAND and XOR Implementations Combinational Design Procedure NAND-NAND & NOR-NOR Networks DeMorgan
More informationbus waveforms transport delta and simulation
bus waveforms transport delta and simulation Time Modelling and Data Flow Descriptions Modeling time in VHDL Different models of time delay Specify timing requirement Data flow descriptions Signal resolution
More informationEFFICIENT OBSERVABILITY ENHANCEMENT TECHNIQUES FOR POST-SILICON VALIDATION AND DEBUG
EFFICIENT OBSERVABILITY ENHANCEMENT TECHNIQUES FOR POST-SILICON VALIDATION AND DEBUG By KANAD BASU A DISSERTATION PRESENTED TO THE GRADUATE SCHOOL OF THE UNIVERSITY OF FLORIDA IN PARTIAL FULFILLMENT OF
More informationUC Berkeley CS61C : Machine Structures
inst.eecs.berkeley.edu/~cs61c UC Berkeley CS61C : Machine Structures Lecture 22 Representations of Combinatorial Logic Circuits Lecturer SOE Dan Garcia www.cs.berkeley.edu/~ddgarcia 100 MPG Car contest!
More informationDigital. Design. R. Ananda Natarajan B C D
Digital E A B C D 0 1 2 3 4 5 6 Design 7 8 9 10 11 12 13 14 15 Y R. Ananda Natarajan Digital Design Digital Design R. ANANDA NATARAJAN Professor Department of Electronics and Instrumentation Engineering
More informationCourse Overview. Course Overview
Course Overview Where does this course fit into the Electrical Engineering curriculum? Page 5 Course Overview Where does this course fit into the Computer Engineering curriculum? Page 6 3 Course Content
More informationCHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT
CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER CONTENTS 3.1 Introduction to Basic Gates 3.2 Analysing A Combinational Logic Circuit 3.3 Design A Combinational Logic Circuit From Boolean Expression
More informationLarger 5 & 6variable Karnaugh maps
Larger 5 & 6variable Karnaugh maps Larger Karnaugh maps reduce larger logic designs. How large is large enough? That depends on the number of inputs, fan-ins, to the logic circuit under consideration.
More informationIn this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions
In this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions Dr Pete Sedcole Department of E&E Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/ (Floyd 3.1 3.6, 4.1) (Tocci 3.1 3.9)
More informationDigital Logic Circuits
Digital Logic Circuits Lecture 5 Section 2.4 Robb T. Koether Hampden-Sydney College Wed, Jan 23, 2013 Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, 2013 1 / 25 1 Logic Gates
More informationFPGA IMPLENTATION OF REVERSIBLE FLOATING POINT MULTIPLIER USING CSA
FPGA IMPLENTATION OF REVERSIBLE FLOATING POINT MULTIPLIER USING CSA Vidya Devi M 1, Lakshmisagar H S 1 1 Assistant Professor, Department of Electronics and Communication BMS Institute of Technology,Bangalore
More informationG53CLP Constraint Logic Programming
G53CLP Constraint Logic Programming Dr Rong Qu Modeling CSPs Case Study I Constraint Programming... represents one of the closest approaches computer science has yet made to the Holy Grail of programming:
More informationNumber system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished
Number system: the system used to count discrete units is called number system Decimal system: the number system that contains 10 distinguished symbols that is 0-9 or digits is called decimal system. As
More informationEECS 150 Homework 4 Solutions Fall 2008
Problem 1: You have a 100 MHz clock, and need to generate 3 separate clocks at different frequencies: 20 MHz, 1kHz, and 1Hz. How many flip flops do you need to implement each clock if you use: a) a ring
More information1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6)
CSE 493/593 Test 2 Fall 2011 Solution 1. Short answer questions. (30) a. What impact does increasing the length of a transistor have on power and delay? Why? (6) Decreasing of W to make the gate slower,
More informationTECH 3232 Fall 2010 Lab #1 Into To Digital Circuits. To review basic logic gates and digital logic circuit construction and testing.
TECH 3232 Fall 2010 Lab #1 Into To Digital Circuits Name: Purpose: To review basic logic gates and digital logic circuit construction and testing. Introduction: The most common way to connect circuits
More informationRT-level Fault Simulation Based on Symbolic Propagation
RT-level Fault Simulation Based on Symbolic Propagation Ozgur Sinanoglu and Alex Orailoglu Computer Science and Engineering Department University of California, San Diego La Jolla, CA 92093 fozgur, alexg@cs.ucsd.edu
More informationPositive and Negative Logic
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 4 Lecture Title:
More informationUsing KenKen to Build Reasoning Skills 1
1 INTRODUCTION Using KenKen to Build Reasoning Skills 1 Harold Reiter Department of Mathematics, University of North Carolina Charlotte, Charlotte, NC 28223, USA hbreiter@email.uncc.edu John Thornton Charlotte,
More informationDigital Fundamentals. Lab 4 EX-OR Circuits & Combinational Circuit Design
Richland College School of Engineering & Technology Rev. 0 B. Donham Rev. 1 (7/2003) J. Horne Rev. 2 (1/2008) J. Bradbury Digital Fundamentals CETT 1425 Lab 4 EX-OR Circuits & Combinational Circuit Design
More informationand not if x >= 0 and x < 10: print("x is a single digit") &
LOGIC OPERATIONS Logic operations We have alread seen kewords or, and, not used in Pthon Had a specific purpose Boolean epressions. For eample: if >= and < : print(" is a single digit") Pthon has a set
More informationLogic diagram: a graphical representation of a circuit
LOGIC AND GATES Introduction to Logic (1) Logic diagram: a graphical representation of a circuit Each type of gate is represented by a specific graphical symbol Truth table: defines the function of a gate
More information