Digital Logic Circuits
|
|
- Juliana Rich
- 6 years ago
- Views:
Transcription
1 Digital Logic Circuits Lecture 5 Section 2.4 Robb T. Koether Hampden-Sydney College Wed, Jan 23, 2013 Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
2 1 Logic Gates 2 Normal Forms 3 Designing Circuits 4 Assignment Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
3 Outline 1 Logic Gates 2 Normal Forms 3 Designing Circuits 4 Assignment Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
4 Logic Gates There are three basic gates. AND-gate OR-gate NOT-gate Two other gates. NAND-gate NOR-gate Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
5 AND-Gate p q Output An AND-gate. The output is 1 if both inputs are 1. The output is 0 if either input is 0. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
6 OR-Gate p q Output An OR-gate. The output is 1 if either input is 1. The output is 0 if both inputs are 0. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
7 NOT-Gate p Output A NOT-gate. The output is 1 if the input is 0. The output is 0 if the input is 1. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
8 NAND-Gate p q Output An NAND-gate. The output is 0 if both inputs are 1. The output is 1 if either input is 0. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
9 NOR-Gate p q Output An NOR-gate. The output is 0 if either input is 1. The output is 1 if both inputs are 0. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
10 Outline 1 Logic Gates 2 Normal Forms 3 Designing Circuits 4 Assignment Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
11 Disjunctive Normal Form A logical expression is in disjunctive normal form (DNF) if It is a disjunction of clauses, Each clause if a conjunction of variables and negations of variables. Each variable or its negation appears in each clause exactly once. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
12 Example p q (p q) ( p q) ( p q). p q (p q) ( p q). p q (p q) ( p q) ( p q). p q p q. What are disjunctive normal forms for T and F? Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
13 Conjunctive Normal Form A logical expression is in conjunctive normal form (CNF) if It is a conjunction of clauses, Each clause if a disjunction of variables and negations of variables. Each variable or its negation appears in each clause exactly once. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
14 Example p q p q. p q (p q) ( p q). p q p q. p q (p q) ( p q) ( p q). What are conjunctive normal forms for T and F? Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
15 Outline 1 Logic Gates 2 Normal Forms 3 Designing Circuits 4 Assignment Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
16 Output Tables Input Output An output table shows the output of a logical function for every possible combination of inputs. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
17 Designing Circuits To design a circuit that represents a logical function, Write an output table for the circuit. The table reveals the DNF form of the function. Write the logical expression and simplify it, if possible. Draw the circuit using AND-gates, OR-gates, and NOT-gates (and NAND-gates and NOR-gates). Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
18 Example Input Output Design a circuit for the above function (which is (p q)). Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
19 Example Design a circuit for (p q) (q r). Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
20 Example Input p q r Output Produce the output table for (p q) (q r). Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
21 Example Based on the output table, the DNF of (p q) (q r) is (p q r) ( p q r) ( p q r). I do not see any way to simplify this. Draw the circuit. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
22 Example Design a logic circuit for (p q) ( q r) r. Use the conjunctive normal form of (p q) ( q r) r to design a circuit. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
23 Outline 1 Logic Gates 2 Normal Forms 3 Designing Circuits 4 Assignment Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
24 Assignment Assignment Read Section 2.4, pages Exercises 1, 2, 5, 6, 9, 10, 15, 17, 18, 19, 24, 25, 32, page 65. Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
25 Collected Homework 1 Collected Homework 1 Page 37, Exercises 15, 42. Page 49, Exercises 6, 17. Page 61, Exercises 11, 23. Due at the beginning of class on Thu, Jan 24, Robb T. Koether (Hampden-Sydney College) Digital Logic Circuits Wed, Jan 23, / 25
Counting and Probability
Counting and Probability Lecture 42 Section 9.1 Robb T. Koether Hampden-Sydney College Wed, Apr 9, 2014 Robb T. Koether (Hampden-Sydney College) Counting and Probability Wed, Apr 9, 2014 1 / 17 1 Probability
More informationEnhanced Turing Machines
Enhanced Turing Machines Lecture 28 Sections 10.1-10.2 Robb T. Koether Hampden-Sydney College Wed, Nov 2, 2016 Robb T. Koether (Hampden-Sydney College) Enhanced Turing Machines Wed, Nov 2, 2016 1 / 21
More informationControlling Bias; Types of Variables
Controlling Bias; Types of Variables Lecture 11 Sections 3.5.2, 4.1-4.2 Robb T. Koether Hampden-Sydney College Mon, Feb 6, 2012 Robb T. Koether (Hampden-Sydney College) Controlling Bias;Types of Variables
More informationRecursive Triangle Puzzle
Recursive Triangle Puzzle Lecture 36 Section 14.7 Robb T. Koether Hampden-Sydney College Fri, Dec 7, 2012 Robb T. Koether (Hampden-Sydney College) Recursive Triangle Puzzle Fri, Dec 7, 2012 1 / 17 1 The
More informationSubqueries Lecture 9
Subqueries Lecture 9 Robb T. Koether Hampden-Sydney College Mon, Feb 6, 2012 Robb T. Koether (Hampden-Sydney College) SubqueriesLecture 9 Mon, Feb 6, 2012 1 / 13 1 Subqueries 2 Robb T. Koether (Hampden-Sydney
More informationPointers. The Rectangle Game. Robb T. Koether. Hampden-Sydney College. Mon, Jan 21, 2013
Pointers The Rectangle Game Robb T. Koether Hampden-Sydney College Mon, Jan 21, 2013 Robb T. Koether (Hampden-Sydney College) Pointers Mon, Jan 21, 2013 1 / 21 1 Introduction 2 The Game Board 3 The Move
More informationET475 Electronic Circuit Design I [Onsite]
ET475 Electronic Circuit Design I [Onsite] Course Description: This course covers the analysis and design of electronic circuits, and includes a laboratory that utilizes computer-aided software tools for
More informationRectangle Man. Lecture 9. Robb T. Koether. Hampden-Sydney College. Fri, Sep 8, 2017
Rectangle Man Lecture 9 Robb T. Koether Hampden-Sydney College Fri, Sep 8, 2017 Robb T. Koether (Hampden-Sydney College) Rectangle Man Fri, Sep 8, 2017 1 / 18 Outline 1 Drawing Rectangle Man 2 Manipulating
More informationLecture 4&5 CMOS Circuits
Lecture 4&5 CMOS Circuits Xuan Silvia Zhang Washington University in St. Louis http://classes.engineering.wustl.edu/ese566/ Worst-Case V OL 2 3 Outline Combinational Logic (Delay Analysis) Sequential Circuits
More informationLab# 13: Introduction to the Digital Logic
Lab# 13: Introduction to the Digital Logic Revision: October 30, 2007 Print Name: Section: In this lab you will become familiar with Physical and Logical Truth tables. As well as asserted high, asserted
More informationLSN 3 Logic Gates. ECT 224 Digital Computer Fundamentals. Department of Engineering Technology
LSN 3 Logic Gates Department of Engineering Technology LSN 3 Inverter One input and one output Produces a compliment of the input Negation indicator Truth table Active low output In Out 0 1 1 0 Active
More informationLOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output.
LOGIC GATES AND LOGIC CIRCUITS A logic gate is an elementary building block of a Digital Circuit. Most logic gates have two inputs and one output. At any given moment, every terminal is in one of the two
More informationVariables. Lecture 13 Sections Wed, Sep 16, Hampden-Sydney College. Displaying Distributions - Quantitative.
- - Lecture 13 Sections 4.4.1-4.4.3 Hampden-Sydney College Wed, Sep 16, 2009 Outline - 1 2 3 4 5 6 7 Even-numbered - Exercise 4.7, p. 226. According to the National Center for Health Statistics, in the
More informationLogic Design I (17.341) Fall Lecture Outline
Logic Design I (17.341) Fall 2011 Lecture Outline Class # 07 October 31, 2011 / November 07, 2011 Dohn Bowden 1 Today s Lecture Administrative Main Logic Topic Homework 2 Course Admin 3 Administrative
More informationEECS150 - Digital Design Lecture 2 - CMOS
EECS150 - Digital Design Lecture 2 - CMOS August 29, 2002 John Wawrzynek Fall 2002 EECS150 - Lec02-CMOS Page 1 Outline Overview of Physical Implementations CMOS devices Announcements/Break CMOS transistor
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple
More informationOutline. Drawing the Graph. 1 Homework Review. 2 Introduction. 3 Histograms. 4 Histograms on the TI Assignment
Lecture 14 Section 4.4.4 on Hampden-Sydney College Fri, Sep 18, 2009 Outline 1 on 2 3 4 on 5 6 Even-numbered on Exercise 4.25, p. 249. The following is a list of homework scores for two students: Student
More informationThis Figure here illustrates the operation for a 2-input OR gate for all four possible input combinations.
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 5 Lecture Title:
More informationMinute Alarm Clock. David Peled LaGuardia Community College
Minute Alarm Clock Thania Miah, Yogeeta Toramall, Reana Ramkhallawan, & Magi Mohamed Forest Hills High School, and High School for Health Professions and Human Services Thani_13@yahoo.com, yogeeta875@yahoo.com,
More informationLecture 2: Digital Logic Basis
Lecture 2: Digital Logic Basis Xufeng Kou School of Information Science and Technology ShanghaiTech University 1 Outline Truth Table Basic Logic Operation and Gates Logic Circuits NOR Gates and NAND Gates
More informationEMT1250 LABORATORY EXPERIMENT. EXPERIMENT # 4: Combinational Logic Circuits. Name: Date:
EXPERIMENT # 4: Combinational Logic Circuits Name: Date: Equipment/Parts Needed: 5V DC Power Supply Digital Trainer (Logic Probe) Breadboard DIP Switch 7400 NAND gate 7402 NOR gate 7404 Inverter 7408 AND
More informationOutline. transistors logic gates. on numbers on strings. writing numbers in words algorithm flowchart code
Outline 1 Digital Systems transistors logic gates 2 Intrinsic Operations on numbers on strings 3 Dictionaries and Conditionals writing numbers in words algorithm flowchart code 4 Summary + Assignments
More informationDigital Fundamentals. Logic gates
Digital Fundamentals Logic gates Objectives Describe the operation of the inverter, the AND gate, and the OR gate Describe the operation of the NAND gate and the NOR gate Express the operation of the NOT,
More informationComputer Architecture (TT 2012)
Computer Architecture (TT 212) Laws of Attraction aniel Kroening Oxford University, Computer Science epartment Version 1., 212 . Kroening: Computer Architecture (TT 212) 2 . Kroening: Computer Architecture
More informationExercises: Fundamentals of Computer Engineering 1 PAGE: 1
Exercises: Fundamentals of Computer Engineering PAGE: Exercise Minimise the following using the laws of Boolean algebra. f = a + ab + ab.2 f ( ) ( ) ( ) 2 = c bd + bd + ac b + d + cd a + b + ad( b + c)
More informationChapter 3 Digital Logic Structures
Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC
More information2 Logic Gates THE INVERTER. A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs.
2 Logic Gates A logic gate is an electronic circuit which makes logic decisions. It has one output and one or more inputs. THE INVERTER The inverter (NOT circuit) performs the operation called inversion
More informationMultiple input gates. The AND gate
Multiple input gates Inverters and buffers exhaust the possibilities for single-input gate circuits. What more can be done with a single logic signal but to buffer it or invert it? To explore more logic
More informationEXPERIMENT 12: DIGITAL LOGIC CIRCUITS
EXPERIMENT 12: DIGITAL LOGIC CIRCUITS The purpose of this experiment is to gain some experience in the use of digital logic circuits. These circuits are used extensively in computers and all types of electronic
More informationGoal-Directed Tableaux
Goal-Directed Tableaux Joke Meheus and Kristof De Clercq Centre for Logic and Philosophy of Science University of Ghent, Belgium Joke.Meheus,Kristof.DeClercq@UGent.be October 21, 2008 Abstract This paper
More informationYour Name and ID. (a) ( 3 points) Breadth First Search is complete even if zero step-costs are allowed.
1 UC Davis: Winter 2003 ECS 170 Introduction to Artificial Intelligence Final Examination, Open Text Book and Open Class Notes. Answer All questions on the question paper in the spaces provided Show all
More informationCHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT
CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER CONTENTS 3.1 Introduction to Basic Gates 3.2 Analysing A Combinational Logic Circuit 3.3 Design A Combinational Logic Circuit From Boolean Expression
More informationIntroduction to Digital Logic Missouri S&T University CPE 2210 Exam 1 Logistics
Introduction to Digital Logic Missouri S&T University CPE 2210 Exam 1 Logistics Egemen K. Çetinkaya Egemen K. Çetinkaya Department of Electrical & Computer Engineering Missouri University of Science and
More informationDIGITAL CIRCUITS AND SYSTEMS ASSIGNMENTS 1 SOLUTIONS
DIGITAL CIRCUITS AND SYSTEMS ASSIGNMENTS 1 SOLUTIONS 1. Analog signal varies continuously between two amplitudes over the given interval of time. Between these limits of amplitude and time, the signal
More informationECE380 Digital Logic. Logic values as voltage levels
ECE380 Digital Logic Implementation Technology: NMOS and PMOS Transistors, CMOS logic gates Dr. D. J. Jackson Lecture 13-1 Logic values as voltage levels V ss is the minimum voltage that can exist in the
More informationLecture # 16 Logic with a State Dependent Device. Logic Gates How are they built in practice?
EECS 42 Introduction to Digital Electronics Andrew R. Neureuther These viewgraphs will be handed out in class 1/21/ Lecture # 16 Logic with a State Dependent Device S&O pp. 9-9, 4-6 (read for graphs and
More informationANALOGUE AND DIGITAL ELECTRONICS STUDENT S WORKBOOK U3: DIGITAL ELECTRONICS
NLOGUE ND DIGITL ELECTRONICS STUDENT S WORKBOOK U3: DIGITL ELECTRONICS Joaquim Crisol Llicència D, Generalitat de Catalunya NILE Norwich, pril of 211 Table of contents Table of contents 3 DIGITL ELECTRONICS....
More informationLogical Agents (AIMA - Chapter 7)
Logical Agents (AIMA - Chapter 7) CIS 391 - Intro to AI 1 Outline 1. Wumpus world 2. Logic-based agents 3. Propositional logic Syntax, semantics, inference, validity, equivalence and satifiability Next
More information11/18/2015. Outline. Logical Agents. The Wumpus World. 1. Automating Hunt the Wumpus : A different kind of problem
Outline Logical Agents (AIMA - Chapter 7) 1. Wumpus world 2. Logic-based agents 3. Propositional logic Syntax, semantics, inference, validity, equivalence and satifiability Next Time: Automated Propositional
More informationNotes. 1. Midterm 1 Thursday February 24 in class.
Notes 1. Midterm 1 Thursday February 24 in class. Covers through text Sec. 4.3, topics of HW 4. GSIs will review material in discussion sections prior to the exam. No books at the exam, no cell phones,
More informationMITOCW watch?v=x-ik9yafapo
MITOCW watch?v=x-ik9yafapo The following content is provided under a Creative Commons license. Your support will help MIT OpenCourseWare continue to offer high quality educational resources for free. To
More informationDEFENCE: GROSSER BELEG
DEFENCE: GROSSER BELEG Graphical Support for the Design and Evaluation of Configurable Logic Blocks Fredo Erxleben Dresden, 4th June 2015 1 Introduction to the Problem 2 Theoretical Background 3 Design
More informationFall 2017 March 13, Written Homework 4
CS1800 Discrete Structures Profs. Aslam, Gold, & Pavlu Fall 017 March 13, 017 Assigned: Fri Oct 7 017 Due: Wed Nov 8 017 Instructions: Written Homework 4 The assignment has to be uploaded to blackboard
More informationDigital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405
Digital Applications () Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering systems,
More informationDigital Logic and Design (Course Code: EE222) Lecture 14: Combinational Contd.. Decoders/Encoders
Indian Institute of Technology Jodhpur, Year 28 29 Digital Logic and Design (Course Code: EE222) Lecture 4: Combinational Contd.. Decoders/Encoders Course Instructor: Shree Prakash Tiwari Email: sptiwari@iitj.ac.in
More informationUNIVERSITI MALAYSIA PERLIS
UNIVERSITI MALAYSIA PERLIS DIGITAL SYSTEM I (DKT122) LAB 2: LOGIC GATE QUESTION & ANSWER SHEET REPORT MOHAMAD RIZAL BIN ABDUL REJAB SITI ZARINA BINTI MD NAZIRI & SPECIAL THANKS TO : ZULKIFLI HUSIN MOHAMMAD
More informationECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits
Faculty of Engineering ECE 334: Electronic Circuits Lecture 10: Digital CMOS Circuits CMOS Technology Complementary MOS, or CMOS, needs both PMOS and NMOS FET devices for their logic gates to be realized
More informationCS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON
CS/ECE 252: INTRODUCTION TO COMPUTER ENGINEERING UNIVERSITY OF WISCONSIN MADISON Instructor: Andy Phelps TAs: Newsha Ardalani, Peter Ohmann, and Jai Menon Midterm Examination 2 In Class (50 minutes) Wednesday,
More informationTopic: Use Parallel Lines and Transversals. and transversals?
Topic: Use Parallel Lines and Transversals and transversals? Get a calculator, protractor and handouts from the back of the room Fill out your assignment sheet Have your Homework out to be graded Do the
More informationDigital Logic Design ELCT 201
Faculty of Information Engineering and Technology Dr. Haitham Omran and Dr. Wassim Alexan Digital Logic Design ELCT 201 Winter 2017 Midterm Exam Second Chance Please tick the box of your major: IET MET
More informationECE 2300 Digital Logic & Computer Organization
ECE 2300 Digital Logic & Computer Organization Spring 2018 CMOS Logic Lecture 4: 1 NAND Logic Gate X Y (X Y) = NAND Using De Morgan s Law: (X Y) = X +Y X X X +Y = Y Y Also a NAND We can build circuits
More informationLecture 9 Transistors
Lecture 9 Transistors Physics Transistor/transistor logic CMOS logic CA 1947 http://www.extremetech.com/extreme/164301-graphenetransistors-based-on-negative-resistance-could-spell-theend-of-silicon-and-semiconductors
More informationCombinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #14
Combinatorial Logic Design Multiplexers and ALUs CS 64: Computer Organization and Design Logic Lecture #14 Ziad Matni Dept. of Computer Science, UCSB Administrative Remaining on the calendar This supersedes
More informationRun-Ons. College Writing Skills,, 8E and College Writing Skills with Readings,, 8E
Chapter Twenty-Five Run-Ons College Writing Skills,, 8E and College Writing Skills with Readings,, 8E John Langan The Two Types of Run-On Sentences Fused Sentences: They are fused or joined together as
More informationChapter 6 DIFFERENT TYPES OF LOGIC GATES
Chapter 6 DIFFERENT TYPES OF LOGIC GATES Lesson 8 NMOS gates Ch06L8-"Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2 Outline NMOS (n-channel based MOSFETs based circuit) NMOS Features
More informationName EGR 2131 Lab #2 Logic Gates and Boolean Algebra Objectives Equipment and Components Part 1: Reading Pin Diagrams 7400 (TOP VIEW)
Name EGR 23 Lab #2 Logic Gates and Boolean Algebra Objectives ) Become familiar with common logic-gate chips and their pin numbers. 2) Using breadboarded chips, investigate the behavior of NOT (Inverter),
More informationElectronics Basic CMOS digital circuits
Electronics Basic CMOS digital circuits Prof. Márta Rencz, Gábor Takács, Dr. György Bognár, Dr. Péter G. Szabó BME DED October 21, 2014 1 / 30 Introduction The topics covered today: The inverter: the simplest
More informationExercise 1: AND/NAND Logic Functions
Exercise 1: AND/NAND Logic Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the operation of an AND and a NAND logic gate. You will verify your results
More informationLecture Week 4. Homework Voltage Divider Equivalent Circuit Observation Exercise
Lecture Week 4 Homework Voltage Divider Equivalent Circuit Observation Exercise Homework: P6 Prove that the equation relating change in potential energy to voltage is dimensionally consistent, using the
More informationChapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1
Chapter 4: FLIP FLOPS (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT 1 CHAPTER 4 : FLIP FLOPS Programme Learning Outcomes, PLO Upon completion of the programme, graduates
More informationUniversity of Technology
University of Technology Lecturer: Dr. Sinan Majid Course Title: microprocessors 4 th year Lecture 7 & 8 NAND and XOR Implementations Combinational Design Procedure NAND-NAND & NOR-NOR Networks DeMorgan
More informationLecture 16 Sections Tue, Sep 23, 2008
s Lecture 16 Sections 5.3.1-5.3.3 Hampden-Sydney College Tue, Sep 23, 2008 in Outline s in 1 2 3 s 4 5 6 in 7 s Exercise 5.7, p. 312. (a) average (or mean) age for 10 adults in a room is 35 years. A 32-year-old
More informationDEPARTMENT OF PHYSICS PHYS*2040 W'09. Fundamental Electronics and Sensors. Lecturer: Dr. Ralf Gellert MacN 450 Ext
DEPARTMENT OF PHYSICS PHYS*2040 W'09 Fundamental Electronics and Sensors Lecturer: Dr. Ralf Gellert MacN 450 Ext. 53992 ralf@physics.uoguelph.ca Lab Instructor: Andrew Tersigni MacN 023 Ext. 58342 andrew@physics.uoguelph.ca
More informationOdd-Prime Number Detector The table of minterms is represented. Table 13.1
Odd-Prime Number Detector The table of minterms is represented. Table 13.1 Minterm A B C D E 1 0 0 0 0 1 3 0 0 0 1 1 5 0 0 1 0 1 7 0 0 1 1 1 11 0 1 0 1 1 13 0 1 1 0 1 17 1 0 0 0 1 19 1 0 0 1 1 23 1 0 1
More informationCombinational Logic Design CH002
Combinational Logic Design CH002 Figure 2.1 Circuit as a black box with inputs, outputs, and specifications Figure 2.2 Elements and nodes Figure 2.3 Combinational logic circuit Figure 2.4 Two OR implementations
More informationIntroduction. BME208 Logic Circuits Yalçın İŞLER
Introduction BME208 Logic Circuits Yalçın İŞLER islerya@yahoo.com http://me.islerya.com 1 Lecture Three hours a week (three credits) No other sections, please register this section Tuesday: 09:30 12:15
More informationDigital Circuits II Lecture 6. Lab Demonstration 3 Using Altera Quartus II to Determine Simplified Equations & Entering Truth Table into VHDL
Digital Circuits II Lecture 6 Lab Demonstration 3 Using Altera Quartus II to Determine Simplified Equations & Entering Truth Table into VHDL References (Text Book): 1) Digital Electronics, 9 th editon,
More informationCOMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA
COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true
More informationExercise 2: OR/NOR Logic Functions
Exercise 2: OR/NOR Logic Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to determine the operation of an OR and a NOR logic gate. You will verify your results by generating
More informationIn this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions
In this lecture: Lecture 3: Basic Logic Gates & Boolean Expressions Dr Pete Sedcole Department of E&E Engineering Imperial College London http://cas.ee.ic.ac.uk/~nps/ (Floyd 3.1 3.6, 4.1) (Tocci 3.1 3.9)
More informationDigital Logic Circuits
Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals
More informationExercise 1: EXCLUSIVE OR/NOR Gate Functions
EXCLUSIVE-OR/NOR Gates Digital Logic Fundamentals Exercise 1: EXCLUSIVE OR/NOR Gate Functions EXERCISE OBJECTIVE When you have completed this exercise, you will be able to demonstrate the operation of
More informationBCD Adder. Lecture 21 1
BCD Adder -BCD adder A 4-bit binary adder that is capable of adding two 4-bit words having a BCD (binary-coded decimal) format. The result of the addition is a BCD-format 4-bit output word, representing
More informationCS1800 Discrete Structures Fall 2016 Profs. Aslam, Gold, Ossowski, Pavlu, & Sprague 7 November, CS1800 Discrete Structures Midterm Version C
CS1800 Discrete Structures Fall 2016 Profs. Aslam, Gold, Ossowski, Pavlu, & Sprague 7 November, 2016 CS1800 Discrete Structures Midterm Version C Instructions: 1. The exam is closed book and closed notes.
More informationAnalog, Digital, and Logic
Analog, Digital, and Logic Analog and Digital A/D and D/A conversion Prof Carruthers (ECE @ BU) EK307 Notes Summer 2018 116 / 264 Analog and Digital Digital and Analog There are 10 kinds of people: those
More informationCombinational Logic. Rab Nawaz Khan Jadoon DCS. Lecturer COMSATS Lahore Pakistan. Department of Computer Science
Combinational Logic Rab Nawaz Khan Jadoon DCS COMSATS Institute of Information Technology Lecturer COMSATS Lahore Pakistan Digital Logic and Computer Design 2 Combinational logic A combinational circuit
More informationECE/CoE 0132: FETs and Gates
ECE/CoE 0132: FETs and Gates Kartik Mohanram September 6, 2017 1 Physical properties of gates Over the next 2 lectures, we will discuss some of the physical characteristics of integrated circuits. We will
More informationAppendix B Page 1 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN ASSIGNMENT (TOP VIEWS)
Appendix B Page 1 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN ASSIGNMENT (TOP VIEWS) See page 3 See page 3 See page 7 See page 14 See page 9 See page 16 See page 10 TEXAS INSTRUMENTS LTD have given their
More informationDigital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405
Digital Applications (CETT 1415) Credit: 4 semester credit hours (3 hours lecture, 4 hours lab) Prerequisite: CETT 1403 & CETT 1405 Course Description This course covers digital techniques and numbering
More informationEECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics
EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics I. OVERVIEW I.A Combinational vs. Sequential Logic Combinational Logic (everything so far): Outputs depend entirely on
More informationLECTURE 7. OPERATIONAL AMPLIFIERS (PART 2)
CIRCUITS by Ulaby & Maharbiz All rights reserved. Do not reproduce or distribute. LECTURE 7. OPERATIONAL AMPLIFIERS (PART 2) 07/16/2013 ECE225 CIRCUIT ANALYSIS All rights reserved. Do not copy or distribute.
More informationPractice Midterm Exam 5
CS103 Spring 2018 Practice Midterm Exam 5 Dress Rehearsal exam This exam is closed-book and closed-computer. You may have a double-sided, 8.5 11 sheet of notes with you when you take this exam. You may
More information(CSC-3501) Lecture 6 (31 Jan 2008) Seung-Jong Park (Jay) CSC S.J. Park. Announcement
Seung-Jong Park (Jay) http://www.csc.lsu.edu/~sjpark Computer Architecture (CSC-3501) Lecture 6 (31 Jan 2008) 1 Announcement 2 1 Reminder A logic circuit is composed of: Inputs Outputs Functional specification
More informationE-Tec Module Part No
E-Tec Module Part No.108227 1. Additional programs for the fischertechnik Electronics Module For fans of digital technology, these additional functions are provided in the "E-Tec module". Four additional
More informationUNIT III. Designing Combinatorial Circuits. Adders
UNIT III Designing Combinatorial Circuits The design of a combinational circuit starts from the verbal outline of the problem and ends with a logic circuit diagram or a set of Boolean functions from which
More informationCombinational logic. ! Regular logic: multiplexers, decoders, LUTs and FPGAs. ! Switches, basic logic and truth tables, logic functions
Combinational logic! Switches, basic logic and truth tables, logic functions! Algebraic expressions to gates! Mapping to different gates! Discrete logic gate components (used in labs and 2)! Canonical
More informationA LOW POWER SINGLE PHASE CLOCK DISTRIBUTION USING 4/5 PRESCALER TECHNIQUE
A LOW POWER SINGLE PHASE CLOCK DISTRIBUTION USING 4/5 PRESCALER TECHNIQUE MS. V.NIVEDITHA 1,D.MARUTHI KUMAR 2 1 PG Scholar in M.Tech, 2 Assistant Professor, Dept. of E.C.E,Srinivasa Ramanujan Institute
More informationSeries-Parallel Circuits
Series-Parallel Circuits INTRODUCTION A series-parallel configuration is one that is formed by a combination of series and parallel elements. A complex configuration is one in which none of the elements
More informationElectrical Engineering 40 Introduction to Microelectronic Circuits
Electrical Engineering 40 Introduction to Microelectronic Circuits Instructor: Prof. Andy Neureuther EECS Department University of California, Berkeley Lecture 1, Slide 1 Introduction Instructor: Prof.
More informationTHE UNIVERSITY OF TRINIDAD & TOBAGO
THE UNIVERSITY OF TRINIDAD & TOBAGO FINAL ASSESSMENT/EXAMINATIONS APRIL/MAY 2014 Course Code and Title: Digital Electronics Programme: Communications Engineering Technology Diploma Date: 16 th April 2014
More informationSuper Mario. Martin Ivanov ETH Zürich 5/27/2015 1
Super Mario Martin Ivanov ETH Zürich 5/27/2015 1 Super Mario Crash Course 1. Goal 2. Basic Enemies Goomba Koopa Troopas Piranha Plant 3. Power Ups Super Mushroom Fire Flower Super Start Coins 5/27/2015
More informationLecture 20 November 13, 2014
6.890: Algorithmic Lower Bounds: Fun With Hardness Proofs Fall 2014 Prof. Erik Demaine Lecture 20 November 13, 2014 Scribes: Chennah Heroor 1 Overview This lecture completes our lectures on game characterization.
More informationBME 3512 Bioelectronics Reading Assignments and Homework Problems Spring 2015
The BME 3512 Bioelectronics course is partitioned into essentially seven areas, divided into four tests: Test One - Principles of DC and AC Circuits Review of Basic Concepts and Principles of DC and AC
More informationE2.11/ISE2.22 Digital Electronics II
E2.11/ISE2.22 Digital Electronics II roblem Sheet 6 (uestion ratings: A=Easy,, E=Hard. All students should do questions rated A, B or C as a minimum) 1B+ A full-adder is a symmetric function of its inputs
More informationElektrische Parameter Grundlagen der technischen Informatik
Elektrische Parameter Grundlagen der technischen Informatik Wintersemester 28/9 Folien basierend auf F. Vahid und S. Werner Wintersemester 28/9 Review - Multiple-Output Circuits Many circuits have more
More informationLogic diagram: a graphical representation of a circuit
LOGIC AND GATES Introduction to Logic (1) Logic diagram: a graphical representation of a circuit Each type of gate is represented by a specific graphical symbol Truth table: defines the function of a gate
More informationPositive and Negative Logic
Course: B.Sc. Applied Physical Science (Computer Science) Year & Sem.: IInd Year, Sem - IIIrd Subject: Computer Science Paper No.: IX Paper Title: Computer System Architecture Lecture No.: 4 Lecture Title:
More informationCSE 21 Mathematics for Algorithm and System Analysis
CSE 21 Mathematics for Algorithm and System Analysis Unit 1: Basic Count and List Section 3: Set CSE21: Lecture 3 1 Reminder Piazza forum address: http://piazza.com/ucsd/summer2013/cse21/hom e Notes on
More informationUnit 5 - Operational Amplifiers
X reviewer2@nptel.iitm.ac.in Courses» Integrated Circuits, MOSFETs, OP-Amps and their Unit 5 - Amplifiers Announcements Course Ask a Question Progress Mentor Course outline Introduction to IC Technology
More information8. Combinational MOS Logic Circuits
8. Combinational MOS Introduction Combinational logic circuits, or gates, witch perform Boolean operations on multiple input variables and determine the output as Boolean functions of the inputs, are the
More information