Scan Side Channel Analysis: a New Way for Non-Invasive Reverse Engineering of a VLSI Device

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Jasmine Rodgers
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1 Scan Side Channel Analysis: a New Way for Non-Invasive Reverse Engineering of a VLSI Device Leonid Azriel Technion Israel Institute of Technology May 6, 2015 May 6,

2 Side Channel Attacks Side Channel Attack: Exploits Weaknesses in Algorithm Implementation May 6,

3 Side Channel Attacks Side Channel Attack: Exploits Weaknesses in Algorithm Implementation Simple/Differential Power Analysis (SPA/DPA) key May 6,

4 Side Channel Attacks Side Channel Attack: Exploits Weaknesses in Algorithm Implementation Simple/Differential Power Analysis (SPA/DPA) Timing key May 6,

5 Side Channel Attacks Side Channel Attack: Exploits Weaknesses in Algorithm Implementation Simple/Differential Power Analysis (SPA/DPA) Timing EM Radiation key May 6,

6 Side Channel Attacks Side Channel Attack: Exploits Weaknesses in Algorithm Implementation Simple/Differential Power Analysis (SPA/DPA) Timing EM Radiation Temperature key May 6,

7 Side Channel Attacks Side Channel Attack: Exploits Weaknesses in Algorithm Implementation Simple/Differential Power Analysis (SPA/DPA) Timing EM Radiation Temperature Test Circuits (Scan) key May 6,

8 The Scan Technique May 6,

9 The Scan Technique Sequential Cells (FFs / Latches) May 6,

10 The Scan Technique Scan Insertion May 6,

11 The Scan Technique ATE Scan Shift May 6,

12 The Scan Technique ATE Capture May 6,

13 The Scan Technique ATE Shift-Out May 6,

14 Exploiting Scan - Retrieving Secrets May 6,

15 Exploiting Scan Altering the Flow May 6,

Cross-section Phase 2 Algorithmic Circuit Spec

16 Reverse Engineering of an ASIC Phase 1 Invasive ASIC Circuit Delayering SEM Nanoscale Imaging Cross-section Phase 2 Algorithmic Circuit Spec FSM Extraction Model Checking SAT May 6,

17 Reverse Engineering of an ASIC Phase 1 Invasive ASIC Circuit Delayering SEM Nanoscale Imaging Cross-section Phase 2 Algorithmic Circuit Spec FSM Extraction Model Checking SAT Scan Side Channel makes Phase 1 non-invasive May 6,

18 Unfolding Sequential Circuits with Scan Combinational Logic Scan turns the ASIC to a stateless circuit Mapped to the Boolean Function Learning problem: {0,1} n {0,1} n Exhaustive Search: Extract the Truth Table by running queries for all inputs Exponential Size May 6,

19 Unfolding Sequential Circuits with Scan Combinational Logic F = Scan turns the ASIC to a stateless circuit Mapped to the Boolean Function Learning problem: {0,1} n {0,1} n Exhaustive Search: Extract the Truth Table by running queries for all inputs Exponential Size: 2Number of Registers May 6,

Unfolding Sequential Circuits with Scan 0 1 0 0 0 Combinational Logic F = 1 1 0 0 1 0 1 1.

20 Unfolding Sequential Circuits with Scan Combinational Logic F = Scan turns the ASIC to a stateless circuit Mapped to the Boolean Function Learning problem: {0,1} n {0,1} n Exhaustive Search: Extract the Truth Table by running queries for all inputs Exponential Size: 2 n May 6,

Shannon Effect Shannon Effect: almost all Boolean functions have a complexity close to the maximal possible (~O(2 n )) for the uniform probability distribution

21 Shannon Effect Shannon Effect: almost all Boolean functions have a complexity close to the maximal possible (~O(2 n )) for the uniform probability distribution Corollary: For large n, almost all Boolean functions are not realizable in VLSI technology 22 n functions Search space for realizable digital circuits May 6,

22 Limited Transitive Fan-in In practice, logic cones have limited number of inputs: Transitive Fan In = K May 6,

23 Algorithm for Limited Transitive Fan-in Suppose F(0) = 0 (simple extension to any F) Example for K = 3: Testing all values of input v with Hamming Weight 3 or less covers all combinations of {a,b,c} v 0 0 a 0 b 0 c Runtime ~ n K F i May 6,

24 Transitive Fan-in Statistics for ITC 99 benchmark Number of registers and outputs Cumulative Percentage Fan In May 6,

25 Locality Hierarchical structure loose connectivity between blocks: clustering Physical locality: adjacent registers in the chain are likely to belong to the same function Often the same sub-circuit is shared by a few logic cones May 6,

26 Incremental K-Bounded Search K=0 K=1 K=K init = Boolean cube May 6,

27 Incremental K-Bounded Search K=0 K=1 K=K init = Boolean cube = Implicant: a cube, for which F i =1 for some i May 6,

28 Incremental K-Bounded Search K=0 K=1 K=K init K=K init +K step May 6,

29 Incremental K-Bounded Search K=0 K=1 K=K init K=K init +K step K=K init +i*k step Continue while there is a change May 6,

30 Example: Arithmetic Circuits Number of probes ESoTT KSoTT/CSoTT ISoTT ESoTT KSoTT/CSoTT ISoTT Space ESoTT KSoTT (bound) CSoTT/ISoTT ESoTT KSoTT (bound) CSoTT/ISoTT N Adder N Multiplier May 6,

31 Pipelined Accumulator ESoTT KSoTT/CSoTT ISoTT ESoTT KSoTT (bound) CSoTT/ISoTT + Number of probes Space N (~Width*Depth) Runtime N (~Width*Depth) Space May 6,

32 Summary Reverse Engineering can be non-invasive Scan Side Channel is a security and IP protection threat Polynomial time reconstruction is possible thanks to the limited transitive fan-in Additional accuracy is achieved with incremental heuristic based algorithm May 6,

33 Future Work Enhancing the algorithms Machine Learning PAC learning Overcoming Practical Limitations Compression, Masking, Protection Methods Hide the function without sacrificing testability Finding Hardware Trojans Detecting mismatches with scan May 6,

34 Thanks! May 6,

Data Compression via Logic Synthesis

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