VLSI System Testing. Outline
|
|
- Claribel James
- 6 years ago
- Views:
Transcription
1 ECE 538 VLSI System Testing Krish Chakrabarty System-on-Chip (SOC) Testing ECE 538 Krish Chakrabarty 1 Outline Motivation for modular testing of SOCs Wrapper design IEEE 1500 Standard Optimization Test access mechanism design and optimization Test scheduling Exploiting port scalability to test embedded cores at multiple data rates Virtual TAMs Matching ATE data rates to scan frequencies of embedded cores Conclusions ECE 538 Krish Chakrabarty 2 1
2 Motivation System-on-chip (SOC) integrated circuits based on embedded intellectual property (IP) cores are now commonplace SOCs include processors, memories, peripheral devices, IP cores, analog cores Low cost, fast time-to-market, high performance, low power Manufacturing test needed to detect manufacturing defects Manufacturing! cost! Test cost! ECE 538 Krish Chakrabarty 3 System-on-Chip (SOC) Test access is limited Test sets must be transported to embedded logic ECE 538 Krish Chakrabarty 4 2
3 0 Shorten production cycles, and increasing complexity of modern electronic systems has forced designers to employ reuse based designs approaches. 0 System-on-Chip (SOC) is an example of such reuse based design approach where pre-designed, pre-verified cores are integrated into a system. SOC CPU2 RAM RAM T DSP Tests T I/O DSP CPU1 I/O T CPU1 T CPU2 ECE 538 Krish Chakrabarty 5 IC design and test development Core provider Core design and test development IC provider IC manufacturing IC testing System integrator SOB design and test development SOB manufacturing System integrator SOC design and test development SOC manufacturing SOB testing SOC testing ECE 538 Krish Chakrabarty 6 3
4 0 Test access mechanism (TAM) 0 An ATE is used to transport the test stimuli to the SOC. The produced responses are transported back to the ATE where they are compared with the expected responses. 0 Memory cores are usually tested using a built-in self-test Test responses Test stimuli CPU2 RAM RAM Expected test responses TAM ATE DSP CPU1 SOC I/O ATE ECE 538 Krish Chakrabarty 7 Modular Testing Test embedded cores using patterns provided by core vendor (test reuse) Test access mechanisms (TAMs) needed for test data transport: TAMs impact test time and test cost Test wrappers translate test data supplied by TAMs TAM optimization and test scheduling are critical ITRS 05: Test data volume and testing time in 2010 will 30X that for today s chips Automatic Test! Equipment (ATE)! SOC Embedded core Embedded core TAM Embedded core Wrapper TAM ECE 538 Krish Chakrabarty 8 4
5 Test Access Problem Plug-and-Play" " " " " " " " " " " " " " " " " Tester" " " " " " " " " 1. How to isolate cores?" 2. How to get patterns to cores?" ECE 538 Krish Chakrabarty 9 Test Scheduling Test scheduling determines sequence of core tests on the TAMs Avoid test resource conflicts Minimize testing time Ineffective scheduling can increase tester data volume: Idle bits Idle bits" Schedule" Core 1! Core 2" Core 4" Time" Core 5! ECE 538 Krish Chakrabarty 10 5
6 Test Planning Optimizing test access to cores and scheduling test hardware Test hardware planning! Test software planning! Core import! Core integration! Test wrapper! & TAM design! Top-level DFT! Test control blocks! IEEE ! Core test import! Top-level ATPG! Glue logic, soft cores! Test wrappers! Test scheduling! Test assembly! ECE 538 Krish Chakrabarty 11 IEEE 1500 Core Test Standard Goals Define test interface between core and SOC Core isolation Plug-and-play protocols Scope Standardize core isolation protocols and test modes TAM design Type of test to be applied Test scheduling ECE 538 Krish Chakrabarty 12 6
7 IEEE 1500 Wrapper Wrapper Modes: (1) Normal; (2) Serial Test; (3) 1-N Test; (4) Bypass; (5) Isolation; (6) Extest Marinissen et al., On IEEE P1500's Standard for Embedded Core Test, Journal of Electronic Testing: Theory and Applications, vol. 18, Aug 2002 ECE 538 Krish Chakrabarty 13 Wrapper Boundary Cells ECE 538 Krish Chakrabarty 14 7
8 Wrapper Usage ECE 538 Krish Chakrabarty 15 Wrapped Embedded Cores ECE 538 Krish Chakrabarty 16 8
9 Wrapper Operation Modes (I) Normal Mode Serial Bypass Mode ECE 538 Krish Chakrabarty 17 Wrapper Operation Modes (II) Serial Internal Test Mode Serial External Test Mode ECE 538 Krish Chakrabarty 18 9
10 Wrapper Operation Modes (III) Parallel Internal Test Mode Parallel External ECE 538 Krish Chakrabarty 19 Test Wrapper Optimization Priority 1: Balanced Wrapper Scan Chains Core" Core" 4 FF! 8 FF! Wrapper! 4 FF! 8 FF! Wrapper! Unbalanced! Balanced! Minimize length of longest wrapper scan in/out chain ECE 538 Krish Chakrabarty 20 10
11 Reducing TAM Width Priority 2: Minimize wrapper scan chains created Scan chain 32 FF! I" I" 8 FF! O" I" 8 FF! O" 4 Wrapper scan chains! I" 8 FF! Scan chain 32 FF! 2 Wrapper scan chains! I" I" I" I" 8 FF! 8 FF! 8 FF! O" O" ECE 538 Krish Chakrabarty 21 Longest wrapper scan chain" Two-Priority Wrapper Design Algorithm TAM width" 1. Minimize length of longest wrapper scan in/out chain 2. Minimize number of wrapper scan chains Design_wrapper algorithm uses the BFD heuristic for Bin Design ECE 538 Krish Chakrabarty 22 11
12 Test Access Mechanisms Types of TAMs Multiplexed access [Immaneni, ITC 90] Reuse system bus [Harrod, ITC 99] Transparent paths [Ghosh, DAC 98] Isolation rings [Whetsel, ITC 97] Test Bus [Varma, ITC 98] Test Rail [Marinissen, ITC 98] C1" C2" C3" Multi-! plexed! C1" C2" C3" Daisy-! chain! C1" C2" C3" Distri-! bution! ECE 538 Krish Chakrabarty Partial isolation rings! 2. Multiplexing! TAM Design Core A! Core B! ECE 538 Krish Chakrabarty 24 12
13 TAM Design 3. Core Transparency! Core A! Core B! ECE 538 Krish Chakrabarty 25 Test Bus Architecture Architecture Schedule: Serial A B C D E F Combination of multiplexing and distribution Supports only serial schedule Core-external testing is cumbersome or impossible ECE 538 Krish Chakrabarty 26 13
14 TestRail Architecture Combination of Daisychain and Distribution architectures Cores connected to a TestRail can be tested simultaneously as well as sequentially Multiple wrappers can be activated simultaneously for Extest TestRails can be either fixed-width or flexible-width Fixed-width TestRails Flexible-width TestRails C1" C2" C3" C1" C2" C3" w 1 " w 2 " C1" C2" W" C1" C2" ECE 538 Krish Chakrabarty 27 Step-by-Step Approach to Wrapper/TAM Co-optimization 1. P W : Wrapper design 2. P AW : Core assignment + P W 3. P PAW : TAM width partitioning + P AW 4. P NPAW : Number of TAMs + P PAW W 3 " W 2 " W 1 " TAMs! IP" IP" IP" Wrapper! Wrapper! Wrapper! ECE 538 Krish Chakrabarty 28 14
15 Mathematical Programming Model for TAM Partitioning Variable x ij = 1, if core i assigned to TAM j Testing time of core i on TAM width w j = T i (w j ) Testing time on TAM j = Σ i T i (w j ) x ij Objective: Minimize T = max j Σ i T i (w j ) x ij Constraints 1. Σ i x ij = 1, every core connected to exactly one TAM 2. Σ i w j = W, total TAM width is W 3. w j w max, maximum width of any TAM is w max ECE 538 Krish Chakrabarty 29 TAM Design and Test Scheduling Given the test set parameters for the cores and the total TAM width W Assign a part of W to each core, design a wrapper for each core, and determine the test schedule, Such that W is not exceeded at any time and Testing time is minimized ECE 538 Krish Chakrabarty 30 15
16 Architectures Determine Schedules Slide provided by Erik Jan Marinissen, Philips Research Labs ECE 538 Krish Chakrabarty 31 Rectangle Model for Test Buses Three test buses Each core on same bus gets equal, fixed TAM width Bus 1! Core 1! Core 3! Core 9! Core 8! Bus 2! Core 2! Core 4! Bus 3! Core 5! Core 6! Core 7! ECE 538 Krish Chakrabarty 32 16
17 Rectangle Representation Testing time T i (w j ) for Core i and TAM width j Rectangle R ij Set of rectangles R i for each core Collection of rectangles R for SOC Set R i of rectangles for Core i T i (w j ) Collection R w j ECE 538 Krish Chakrabarty 33 Rectangle Packing Problem Given collection R of rectangle sets for the SOC cores, Select one rectangle R ij for each Core i Pack the selected rectangles into a bin of fixed height, Such that bin width is minimized Collection R Height Core 1 Core 2 Width Core 3 ECE 538 Krish Chakrabarty 34 17
18 Packed Bin = TAM Design + Test Schedule Rectangle area = tester " memory for core test" Empty space = wasted " tester memory" Bin height = " total TAM width" Core 2" Core 1" Core 8" Core 4" Core 3" Core 5" Core 7" Core 6" Bin width = SOC testing time" ECE 538 Krish Chakrabarty 35 Preferred TAM Widths Testing time Preferred TAM width TAM width Pareto-optimal width Only Pareto-optimal TAM widths are considered Procedure: Tests are scheduled at current time in decreasing order of preferred TAM width until no TAM width remains ECE 538 Krish Chakrabarty 36 18
19 Non-Preferred Rectangles: Fill Idle Time Next_time" Core 3! Core 3! Total TAM width" Core 2-P! Core 1-P! Core 2-P! Core 1-P! Core 2! Core 3-P! Core 1! Current_time" ECE 538 Krish Chakrabarty 37 Increasing Current TAM Widths Total TAM width" Core 4-P" W_available" Core 1-P" Core 3" Core 3-P" Core 2-P" Current_time" Current_time" Current_time" Modify current rectangle that will benefit the most from an increase in TAM width If idle time is inevitable, advance Current_time and repeat procedure from the start ECE 538 Krish Chakrabarty 38 19
20 Preemption Core 2" Core 8" Core 4" Core 8" Core 7" Core 5" Core 1" Core 3" Core 6" 1. Break up a long test to fill in idle time gaps in schedule" 2. Break up a test to avoid a potential conflict" ECE 538 Krish Chakrabarty 39 Power Constraints 1. Excessive test concurrency can burn the SOC" 2. Cores that do not operate together may be " tested together " Power consumption" Core 2" Core 1" Core 8" Core 8" Core 5" Core 4" Core 7" Core 3" Core 6" ECE 538 Krish Chakrabarty 40 20
21 Precedence Relationships 1. Memory BIST before external test" 2. Tests that detect more faults applied first" 3. Shorter tests first" Example: Core 4 must complete before Core 6 begins" Core 2" Core 8" Core 4" Core 5" Core 7" Core 1" Core 3" Core 6" ECE 538 Krish Chakrabarty 41 ITC 2002 SOC Test Benchmarks Initiative led by Philips Research Labs and Duke University Freely downloadable through Internet Currently 12 SOC benchmarks 5 from academic contributors 7 from industrial contributors Awareness, Interest, Usage reflector with 43 subscribers Awareness panel session at TECS 02: How Useful Are The ITC 02 SOC Test Benchmarks? Panel report in IEEE Design & Test of Computers 10/2002 Special session at ITC 02 + papers in other sessions Numerous papers using the benchmarks in journals and conferences Extensions added by others (layout data, power consumption data, functional interconnects., etc.) ECE 538 Krish Chakrabarty 42 21
22 Current-Generation ATEs Port scalability features Digital speeds of up to 2.5 Gbps Application flexibility Every port of a tester, consisting of multiple channels, can configured at a desired data rate ECE 538 Krish Chakrabarty 43 Virtual TAMs Embedded core test frequency is limited by scan frequency Scan frequencies are low to meet power, routing, and clock skew constraints Virtual TAMs allow use of high frequency ATE pins How can we match fast ATE data rates to slow scan frequencies? ECE 538 Krish Chakrabarty 44 22
23 Bandwidth Matching ATE" High frequency Bandwidth" ATE lines Matching" Low frequency ATE lines 10 low frequency" lines to the cores" ATE pins : W ATE = 4" ATE frequency factor : n = 4" High frequency pins U = 2" Virtual TAM" ECE 538 Krish Chakrabarty 45 Implementation of Bandwidth Matching Low-speed TAM SOC ATE U Serial-In/ Parallelout Registers U U U U Embedded core U U U U Parallel-In/ Serialout Registers High-speed TAM (n = 4) W ATE -U Low-speed TAM ECE 538 Krish Chakrabarty 46 23
24 Selection of U and n Testing of SOC is often dominated by the testing time of bottleneck cores Testing time of SOCs containing bottleneck cores does not decrease for TAM widths greater than W* The lower bound on test time in such SOCs is T* corresponding to TAM width W* ECE 538 Krish Chakrabarty 47 SOCs with Bottleneck Cores SOC W* (bits) T* (clock cycles) u d g p t h f q ECE 538 Krish Chakrabarty 48 24
25 Relationship of U, n and W* U and n should be chosen such that total virtual TAM width W does not exceed W* ECE 538 Krish Chakrabarty 49 Variation of U with n ECE 538 Krish Chakrabarty 50 25
26 U vs n for ITC 02 Benchmarks SOC p34392! W*=36" SOC h953! W*=16" SOC d281! SOC g1023! W*=48" W*=40" ECE 538 Krish Chakrabarty 51 Multiple-Speed TAM Architectures Exploit port-scalability of ATEs Facilitate efficient use of high data-rate tester channels Unlike virtual TAMs, avoid on-chip hardware overhead Reduce testing time of bottleneck cores fast" ATE! slow" SOC! ECE 538 Krish Chakrabarty 52 26
27 Problem Formulation Dual-speed optimization problem Given:! f.r ATE! V! r SOC! Embedded! cores! W-V! Determine the wrapper design, TAM width and test data rate for each! core, and the SOC test schedule such that:! the total number of TAM wires utilized at any moment does not exceed W the number of TAM wires driven at the high data rate does not exceed V the SOC testing time is minimized ECE 538 Krish Chakrabarty 53 Selection of Data Rate for a Core Testing time" r fast" Testing time" f.r TAM width" Core 5 in SOC p93791 TAM width" f =2 V=10 T = μs f =1 W-V=23 T = μs ECE 538 Krish Chakrabarty 54 27
28 Matching Core Scan Frequencies to ATE Data Rates Core A! Core B! Core C! Core D! Baseline! Case 1! TAM width! f = 40MHz! A! B! C! D! f = 80MHz! T = 456 μs! w 1 = 8 f 1 = 40MHz! w 2 = 2, f 2 = 40MHz! Test time! ECE 538 Krish Chakrabarty 55 Matching Core Scan Frequencies to ATE Data Rates Core A! Core B! Core C! Core D! f = 40MHz! f = 80MHz! Baseline! Case 2! TAM width! T = 275 μs! A! C! D! B! w 1 = 8 f 1 = 80MHz! w 1 = 2, f 2 = 40MHz! Test time! ECE 538 Krish Chakrabarty 56 28
29 Matching Core Scan Frequencies to ATE Data Rates Core A! Core B! Core C! Core D! f = 40MHz! f = 80MHz! TAM width! A! B! C! D! w 1 = 5 f 1 = 80MHz! f 2 = 40MHz! w 1 = 5 T = 246 μs! Test time! ECE 538 Krish Chakrabarty 57 Given Problem Statement Test data parameters for N embedded cores Maximum scan frequency f i * for each core i SOC-level TAM width W Determine The number of TAM partitions B Width w j and scan frequency f j of each TAM partition j Assignment of cores to TAM partitions Such that TAM frequency does not exceed the maximum scan frequency of any core assigned to that TAM partition The overall test time is minimized The sum of the widths of all the TAM partitions does not exceed W ECE 538 Krish Chakrabarty 58 29
30 Solution Techniques Lower bound on test time based on geometric arguments (rectangle packing) Integer linear programming Exact optimization method, limited to small problem instances Fast heuristic method Scalable, close to optimal results ECE 538 Krish Chakrabarty 59 Comparison with Baseline (X 100) p22810! (5 frequencies: 10 to 50 MHz)! 300 Test time (μs)! %! LB baseline proposed TAM Width ECE 538 Krish Chakrabarty 60 30
31 (X 100) 12 Test time (μs)! Comparison with Exact Method and Baseline d695! (2 frequencies: 40 MHz and 50 MHz)! ILP TAM Width baseline proposed ECE 538 Krish Chakrabarty 61 Conclusions Test reuse and test time minimization are necessary to reduce test cost for SOCs Wrapper/TAM optimization and test scheduling can reduce test time for core-based SOCs Virtual TAMs offer several advantages for SOC testing On-chip TAM wires are not limited by the number of available pins on the SOC Better utilization of high-speed ATE channels reduces testing times TAM architectures can be designed to match portscalable ATE channels to different scan frequencies of embedded cores ECE 538 Krish Chakrabarty 62 31
Design for Test of Digital Systems TDDC33
ourse Outline Design for Test of Digital Systems TDD33 rik Larsson Department of omputer Science! Introduction; Manufacturing, afer sort, Final test, oard and System Test, Defects, and Faults! Test generation;
More informationRECENT advances in CMOS technology have led to a
120 IEEE TRANSACTIONS ON COMPUTERS, VOL. 56, NO. 1, JANUARY 2007 Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs Anuja Sehgal, Member, IEEE, and Krishnendu Chakrabarty,
More informationVLSI Design Verification and Test Delay Faults II CMPE 646
Path Counting The number of paths can be an exponential function of the # of gates. Parallel multipliers are notorious for having huge numbers of paths. It is possible to efficiently count paths in spite
More informationAn Integrated Framework for Concurrent Test and Wireless Control in Complex SoCs
An Integrated Framework for Concurrent est and Wireless Control in Complex SoCs by Dan Zhao December 2003 A dissertation submitted to the Faculty of the Graduate School of State University of New York
More informationDesign Automation for IEEE P1687
Design Automation for IEEE P1687 Farrokh Ghani Zadegan 1, Urban Ingelsson 1, Gunnar Carlsson 2 and Erik Larsson 1 1 Linköping University, 2 Ericsson AB, Linköping, Sweden Stockholm, Sweden ghanizadegan@ieee.org,
More informationDatorstödd Elektronikkonstruktion
Datorstödd Elektronikkonstruktion [Computer Aided Design of Electronics] Zebo Peng, Petru Eles and Gert Jervan Embedded Systems Laboratory IDA, Linköping University http://www.ida.liu.se/~tdts80/~tdts80
More informationPower-Aware SoC Test Optimization through Dynamic Voltage and Frequency Scaling
Power-Aware SoC Test Optimization through Dynamic Voltage and Frequency Scaling Vijay Sheshadri, Vishwani D. Agrawal and Prathima Agrawal Department of Electrical and Computer Engineering Auburn University
More informationDSP VLSI Design. DSP Systems. Byungin Moon. Yonsei University
Byungin Moon Yonsei University Outline What is a DSP system? Why is important DSP? Advantages of DSP systems over analog systems Example DSP applications Characteristics of DSP systems Sample rates Clock
More informationTest Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 26, NO. 8, AUGUST 2007 1539 Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple
More informationChapter 1 Introduction
Chapter 1 Introduction 1.1 Introduction There are many possible facts because of which the power efficiency is becoming important consideration. The most portable systems used in recent era, which are
More information7. Introduction to mixed-signal testing using the IEEE P standard
7. Introduction to mixed-signal testing using the IEEE P1149.4 standard It was already mentioned in previous chapters that the IEEE 1149.1 standard (BST) was developed with the specific purpose of addressing
More informationIEEE Std Implementation for a XAUI-to-Serial 10-Gbps Transceiver
IEEE Std 1149.6 Implementation for a XAUI-to-Serial 10-Gbps Transceiver Saghir A Shaikh Intel Corporation, San Diego, CA Abstract The design, implementation and verification of IEEE Std 1149.6 IP for a
More informationUsing an FPGA based system for IEEE 1641 waveform generation
Using an FPGA based system for IEEE 1641 waveform generation Colin Baker EADS Test & Services (UK) Ltd 23 25 Cobham Road Wimborne, Dorset, UK colin.baker@eads-ts.com Ashley Hulme EADS Test Engineering
More informationOnline Monitoring for Automotive Sub-systems Using
Online Monitoring for Automotive Sub-systems Using 1149.4 C. Jeffrey, A. Lechner & A. Richardson Centre for Microsystems Engineering, Lancaster University, Lancaster, LA1 4YR, UK 1 Abstract This paper
More informationDebugging a Boundary-Scan I 2 C Script Test with the BusPro - I and I2C Exerciser Software: A Case Study
Debugging a Boundary-Scan I 2 C Script Test with the BusPro - I and I2C Exerciser Software: A Case Study Overview When developing and debugging I 2 C based hardware and software, it is extremely helpful
More informationPolicy-Based RTL Design
Policy-Based RTL Design Bhanu Kapoor and Bernard Murphy bkapoor@atrenta.com Atrenta, Inc., 2001 Gateway Pl. 440W San Jose, CA 95110 Abstract achieving the desired goals. We present a new methodology to
More informationEECS 427 Lecture 21: Design for Test (DFT) Reminders
EECS 427 Lecture 21: Design for Test (DFT) Readings: Insert H.3, CBF Ch 25 EECS 427 F09 Lecture 21 1 Reminders One more deadline Finish your project by Dec. 14 Schematic, layout, simulations, and final
More informationComputer Aided Design of Electronics
Computer Aided Design of Electronics [Datorstödd Elektronikkonstruktion] Zebo Peng, Petru Eles, and Nima Aghaee Embedded Systems Laboratory IDA, Linköping University www.ida.liu.se/~tdts01 Electronic Systems
More informationA GATING SCAN CELL ARCHITECTURE FOR TEST POWER REDUCTION IN VLSI CIRCUITS Ch.Pallavi 1, M.Niraja 2, N.Revathi 3 1,2,3
A GATING SCAN CELL ARCHITECTURE FOR TEST POWER REDUCTION IN VLSI CIRCUITS Ch.Pallavi 1, M.Niraja 2, N.Revathi 3 1,2,3 Assistant Professor, Department of ECE, Siddharth Institute of Engineering & Technology,
More informationFlexible and Modular Approaches to Multi-Device Testing
Flexible and Modular Approaches to Multi-Device Testing by Robin Irwin Aeroflex Test Solutions Introduction Testing time is a significant factor in the overall production time for mobile terminal devices,
More informationVLSI testing Introduction
VLSI testing Introduction Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Dept. of Electrical Engineering Indian Institute of Technology Bombay, Mumbai viren@ee.iitb.ac.in
More informationHello, and welcome to this presentation of the STM32 Digital Filter for Sigma-Delta modulators interface. The features of this interface, which
Hello, and welcome to this presentation of the STM32 Digital Filter for Sigma-Delta modulators interface. The features of this interface, which behaves like ADC with external analog part and configurable
More informationChapter 1 Introduction to VLSI Testing
Chapter 1 Introduction to VLSI Testing 2 Goal of this Lecture l Understand the process of testing l Familiar with terms used in testing l View testing as a problem of economics 3 Introduction to IC Testing
More informationChapter 3 Chip Planning
Chapter 3 Chip Planning 3.1 Introduction to Floorplanning 3. Optimization Goals in Floorplanning 3.3 Terminology 3.4 Floorplan Representations 3.4.1 Floorplan to a Constraint-Graph Pair 3.4. Floorplan
More informationReducing ATE Cost in System-on-Chip Test
Reducing ATE Cost in System-on-Chip Test Ilia Polian Bernd Becker Institute of Computer Science Albert-Ludigs-University Georges-Köhler-Allee 51 79110 Freiburg im Breisgau, Germany email: < polian, becker
More informationA Novel Low-Power Scan Design Technique Using Supply Gating
A Novel Low-Power Scan Design Technique Using Supply Gating S. Bhunia, H. Mahmoodi, S. Mukhopadhyay, D. Ghosh, and K. Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette,
More informationLecture 1: Digital Systems and VLSI
VLSI Design Lecture 1: Digital Systems and VLSI Shaahinhi Hessabi Department of Computer Engineering Sharif University of Technology Adapted with modifications from lecture notes prepared by the book author
More informationDisseny físic. Disseny en Standard Cells. Enric Pastor Rosa M. Badia Ramon Canal DM Tardor DM, Tardor
Disseny físic Disseny en Standard Cells Enric Pastor Rosa M. Badia Ramon Canal DM Tardor 2005 DM, Tardor 2005 1 Design domains (Gajski) Structural Processor, memory ALU, registers Cell Device, gate Transistor
More informationParallel Test Scheduling of 3D Stacked SoCs with Temperature and Time Constraints
IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 5, Issue 4, Ver. II (Jul - Aug. 2015), PP 01-13 e-issn: 2319 4200, p-issn No. : 2319 4197 www.iosrjournals.org Parallel Test Scheduling of
More informationLecture Perspectives. Administrivia
Lecture 29-30 Perspectives Administrivia Final on Friday May 18 12:30-3:30 pm» Location: 251 Hearst Gym Topics all what was covered in class. Review Session Time and Location TBA Lab and hw scores to be
More informationSoC Test Architecture Design and Optimization Considering Power Supply Noise Effects
SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects Feng Yuan and Qiang Xu CUhk REliable computing laboratory (CURE) Dept. of Computer Science & Engineering, The Chinese
More informationShelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores
Shelf Packing to the Design and Optimization of A Power-Aware Multi-Frequency Wrapper Architecture for Modular IP Cores Dan Zhao and Unni Chandran Hideo Fujiwara Center for Advanced Computer Studies Graduate
More informationOptimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling
Manuscript - Main file Click here to download Manuscript: JETTA.tex Click here to view linked References 0 0 0 0 0 Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency
More informationLecture 30. Perspectives. Digital Integrated Circuits Perspectives
Lecture 30 Perspectives Administrivia Final on Friday December 15 8 am Location: 251 Hearst Gym Topics all what was covered in class. Precise reading information will be posted on the web-site Review Session
More informationChapter 20 Circuit Design Methodologies for Test Power Reduction in Nano-Scaled Technologies
Chapter 20 Circuit Design Methodologies for Test Power Reduction in Nano-Scaled Technologies Veena S. Chakravarthi and Swaroop Ghosh Abstract Test power has emerged as an important design concern in nano-scaled
More informationIn the previous chapters, efficient and new methods and. algorithms have been presented in analog fault diagnosis. Also a
118 CHAPTER 6 Mixed Signal Integrated Circuits Testing - A Study 6.0 Introduction In the previous chapters, efficient and new methods and algorithms have been presented in analog fault diagnosis. Also
More informationDigital Integrated CircuitDesign
Digital Integrated CircuitDesign Lecture 13 Building Blocks (Multipliers) Register Adder Shift Register Adib Abrishamifar EE Department IUST Acknowledgement This lecture note has been summarized and categorized
More informationTesting Digital Systems II. Problem: Fault Diagnosis
Testing Digital Systems II Lecture : Logic Diagnosis Instructor: M. Tahoori Copyright 26, M. Tahoori TDSII: Lecture Problem: Fault Diagnosis test patterns Circuit Under Diagnosis (CUD) expected response
More informationExploring the Basics of AC Scan
Page 1 of 8 Exploring the Basics of AC Scan by Alfred L. Crouch, Inovys This in-depth discussion of scan-based testing explores the benefits, implementation, and possible problems of AC scan. Today s large,
More informationTesting Digital Systems II
Lecture : Introduction Instructor: M. Tahoori Copyright 206, M. Tahoori TDS II: Lecture Today s Lecture Logistics Course Outline Review from TDS I Copyright 206, M. Tahoori TDS II: Lecture 2 Lecture Logistics
More informationA Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs
A Flexible Design Methodology for Analog Test Wrappers in Mixed-Signal SOCs Abstract The manufacturing test cost for mixed-signal SOCs is widely recognized to be much higher than that for digital SOCs.
More informationto Moore and McCluskey the following formula calculates this number:
An Introduction To Jtag/Boundary Scan Jtag/Boundary Scan is a test technology. It is the jump from physical access to a board s conductor tracks (necessary for the In-Circuit Test) with all its physical
More informationRuixing Yang
Design of the Power Switching Network Ruixing Yang 15.01.2009 Outline Power Gating implementation styles Sleep transistor power network synthesis Wakeup in-rush current control Wakeup and sleep latency
More informationIntroduction to CMC 3D Test Chip Project
Introduction to CMC 3D Test Chip Project Robert Mallard CMC Microsystems Apr 20, 2011 1 Overview of today s presentation Introduction to the project objectives CMC Why 3D chip stacking? The key to More
More informationAutomated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems
Automated Generation of Built-In Self-Test and Measurement Circuitry for Mixed-Signal Circuits and Systems George J. Starr, Jie Qin, Bradley F. Dutton, Charles E. Stroud, F. Foster Dai and Victor P. Nelson
More informationLow-Power CMOS VLSI Design
Low-Power CMOS VLSI Design ( 范倫達 ), Ph. D. Department of Computer Science, National Chiao Tung University, Taiwan, R.O.C. Fall, 2017 ldvan@cs.nctu.edu.tw http://www.cs.nctu.tw/~ldvan/ Outline Introduction
More informationLow-Power Digital CMOS Design: A Survey
Low-Power Digital CMOS Design: A Survey Krister Landernäs June 4, 2005 Department of Computer Science and Electronics, Mälardalen University Abstract The aim of this document is to provide the reader with
More informationEECS150 - Digital Design Lecture 28 Course Wrap Up. Recap 1
EECS150 - Digital Design Lecture 28 Course Wrap Up Dec. 5, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John Wawrzynek)
More informationDesign A Redundant Binary Multiplier Using Dual Logic Level Technique
Design A Redundant Binary Multiplier Using Dual Logic Level Technique Sreenivasa Rao Assistant Professor, Department of ECE, Santhiram Engineering College, Nandyala, A.P. Jayanthi M.Tech Scholar in VLSI,
More informationDFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers
DFT for Testing High-Performance Pipelined Circuits with Slow-Speed Testers Muhammad Nummer and Manoj Sachdev University of Waterloo, Ontario, Canada mnummer@vlsi.uwaterloo.ca, msachdev@ece.uwaterloo.ca
More informationREVOLUTIONIZING THE COMPUTING LANDSCAPE AND BEYOND.
December 3-6, 2018 Santa Clara Convention Center CA, USA REVOLUTIONIZING THE COMPUTING LANDSCAPE AND BEYOND. https://tmt.knect365.com/risc-v-summit @risc_v ACCELERATING INFERENCING ON THE EDGE WITH RISC-V
More informationEC 1354-Principles of VLSI Design
EC 1354-Principles of VLSI Design UNIT I MOS TRANSISTOR THEORY AND PROCESS TECHNOLOGY PART-A 1. What are the four generations of integrated circuits? 2. Give the advantages of IC. 3. Give the variety of
More informationRun-Length Based Huffman Coding
Chapter 5 Run-Length Based Huffman Coding This chapter presents a multistage encoding technique to reduce the test data volume and test power in scan-based test applications. We have proposed a statistical
More informationChapter 12. Cross-Layer Optimization for Multi- Hop Cognitive Radio Networks
Chapter 12 Cross-Layer Optimization for Multi- Hop Cognitive Radio Networks 1 Outline CR network (CRN) properties Mathematical models at multiple layers Case study 2 Traditional Radio vs CR Traditional
More informationLeakage Power Minimization in Deep-Submicron CMOS circuits
Outline Leakage Power Minimization in Deep-Submicron circuits Politecnico di Torino Dip. di Automatica e Informatica 1019 Torino, Italy enrico.macii@polito.it Introduction. Design for low leakage: Basics.
More informationA Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication
A Level-Encoded Transition Signaling Protocol for High-Throughput Asynchronous Global Communication Peggy B. McGee, Melinda Y. Agyekum, Moustafa M. Mohamed and Steven M. Nowick {pmcgee, melinda, mmohamed,
More informationDesign For Test. VLSI Design I. Design for Test. page 1. What can we do to increase testability?
VLS esign esign for Test esign For Test What can we do to increase ability? He s dead Jim... Overview design for architectures ad-hoc, scan based, built-in in Goal: You are familiar with ability metrics
More informationVideo Enhancement Algorithms on System on Chip
International Journal of Scientific and Research Publications, Volume 2, Issue 4, April 2012 1 Video Enhancement Algorithms on System on Chip Dr.Ch. Ravikumar, Dr. S.K. Srivatsa Abstract- This paper presents
More informationDesign for Test for Digital ICs and Embedded Core Systems. Digital System Testing and Testable Design
Books A. Crouch. Design for Test for Digital ICs and Embedded Core Systems Prentice Hall, 1999. M. Abramovici, M. Breuer, A. Friedman. Digital System Testing and Testable Design Computer Science Press,
More informationEECS 579 Fall What is Testing?
EECS 579 Fall 2001 Recap Text (new): Essentials of Electronic Testing by M. Bushnell & V. Agrawal, Kluwer, Boston, 2000. Class Home Page: http://www.eecs.umich.edu/courses/eecs579 Lecture notes and other
More informationCS 6135 VLSI Physical Design Automation Fall 2003
CS 6135 VLSI Physical Design Automation Fall 2003 1 Course Information Class time: R789 Location: EECS 224 Instructor: Ting-Chi Wang ( ) EECS 643, (03) 5742963 tcwang@cs.nthu.edu.tw Office hours: M56R5
More informationTesting of Complex Digital Chips. Juri Schmidt Advanced Seminar
Testing of Complex Digital Chips Juri Schmidt Advanced Seminar - 11.02.2013 Outline Motivation Why testing is necessary Background Chip manufacturing Yield Reasons for bad Chips Design for Testability
More informationEE241 - Spring 2004 Advanced Digital Integrated Circuits. Announcements. Borivoje Nikolic. Lecture 15 Low-Power Design: Supply Voltage Scaling
EE241 - Spring 2004 Advanced Digital Integrated Circuits Borivoje Nikolic Lecture 15 Low-Power Design: Supply Voltage Scaling Announcements Homework #2 due today Midterm project reports due next Thursday
More informationDESIGN FOR LOW-POWER USING MULTI-PHASE AND MULTI- FREQUENCY CLOCKING
3 rd Int. Conf. CiiT, Molika, Dec.12-15, 2002 31 DESIGN FOR LOW-POWER USING MULTI-PHASE AND MULTI- FREQUENCY CLOCKING M. Stojčev, G. Jovanović Faculty of Electronic Engineering, University of Niš Beogradska
More informationDual Protocol Transceivers Ease the Design of Industrial Interfaces
Dual Protocol Transceivers Ease the Design of Industrial Interfaces Introduction The trend in industrial PC designs towards smaller form factors and more communication versatility is driving the development
More informationIn this lecture, we will look at how different electronic modules communicate with each other. We will consider the following topics:
In this lecture, we will look at how different electronic modules communicate with each other. We will consider the following topics: Links between Digital and Analogue Serial vs Parallel links Flow control
More informationOptimization of energy consumption in a NOC link by using novel data encoding technique
Optimization of energy consumption in a NOC link by using novel data encoding technique Asha J. 1, Rohith P. 1M.Tech, VLSI design and embedded system, RIT, Hassan, Karnataka, India Assistent professor,
More informationNovel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis
Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis N. Banerjee, A. Raychowdhury, S. Bhunia, H. Mahmoodi, and K. Roy School of Electrical and Computer Engineering, Purdue University,
More informationAn Efficient Method for Implementation of Convolution
IAAST ONLINE ISSN 2277-1565 PRINT ISSN 0976-4828 CODEN: IAASCA International Archive of Applied Sciences and Technology IAAST; Vol 4 [2] June 2013: 62-69 2013 Society of Education, India [ISO9001: 2008
More informationDesign for Testability & Design for Debug
EE-382M VLSI II Design for Testability & Design for Debug Bob Molyneaux Mark McDermott Anil Sabbavarapu EE 382M Class Notes Foil # 1 The University of Texas at Austin Agenda Why test? Scan: What is it?
More informationOscillation Ring Test Using Modified State Register Cell For Synchronous Sequential Circuit
I J C T A, 9(15), 2016, pp. 7465-7470 International Science Press Oscillation Ring Test Using Modified State Register Cell For Synchronous Sequential Circuit B. Gobinath* and B. Viswanathan** ABSTRACT
More informationReduction. CSCE 6730 Advanced VLSI Systems. Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are
Lecture e 8: Peak Power Reduction CSCE 6730 Advanced VLSI Systems Instructor: Saraju P. Mohanty, Ph. D. NOTE: The figures, text etc included in slides are borrowed from various books, websites, authors
More informationLab 1.2 Joystick Interface
Lab 1.2 Joystick Interface Lab 1.0 + 1.1 PWM Software/Hardware Design (recap) The previous labs in the 1.x series put you through the following progression: Lab 1.0 You learnt some theory behind how one
More informationTraining Schedule. Robotic System Design using Arduino Platform
Training Schedule Robotic System Design using Arduino Platform Session - 1 Embedded System Design Basics : Scope : To introduce Embedded Systems hardware design fundamentals to students. Processor Selection
More informationSCHEDULING Giovanni De Micheli Stanford University
SCHEDULING Giovanni De Micheli Stanford University Outline The scheduling problem. Scheduling without constraints. Scheduling under timing constraints. Relative scheduling. Scheduling under resource constraints.
More informationAN IMPLEMENTATION OF MULTI-DSP SYSTEM ARCHITECTURE FOR PROCESSING VARIANT LENGTH FRAME FOR WEATHER RADAR
DOI: 10.21917/ime.2018.0096 AN IMPLEMENTATION OF MULTI- SYSTEM ARCHITECTURE FOR PROCESSING VARIANT LENGTH FRAME FOR WEATHER RADAR Min WonJun, Han Il, Kang DokGil and Kim JangSu Institute of Information
More informationInterconnect testing of FPGA
Center for RC eliable omputing Interconnect Testing of FPGA Stanford CRC March 12, 2001 Problem Statement Detecting all faults in FPGA interconnect resources Wire segments Programmable interconnect points
More informationAPPLICATION OF PROGRAMMABLE LOGIC DEVICES FOR ACQUISITION OF ECG SIGNAL WITH PACEMAKER PULSES 1. HISTORY OF PROGRAMMABLE CIRCUITS
JOURNAL OF MEDICAL INFORMATICS & TECHNOLOGIES Vol.4/2002, ISSN 1642-6037 Leszek DREWNIOK *, Janusz ZMUDZINSKI *, Jerzy GALECKA *, Adam GACEK * programmable circuits ECG acquisition with cardiostimulator
More informationCourse Outcome of M.Tech (VLSI Design)
Course Outcome of M.Tech (VLSI Design) PVL108: Device Physics and Technology The students are able to: 1. Understand the basic physics of semiconductor devices and the basics theory of PN junction. 2.
More informationCHAPTER 4 HARDWARE DEVELOPMENT OF STATCOM
74 CHAPTER 4 HARDWARE DEVELOPMENT OF STATCOM 4.1 LABORATARY SETUP OF STATCOM The laboratory setup of the STATCOM consists of the following hardware components: Three phase auto transformer used as a 3
More informationPXI Modules 3066 PXI Multi-Way Active RF Combiner Data Sheet
PXI Modules 3066 PXI Multi-Way Active RF Combiner Data Sheet The most important thing we build is trust 250 MHz to 6 GHz RF signal conditioning module for multi- UE, MIMO and Smartphone testing Four full
More informationEfficient Test Data Compression and Decompression for System-on-a-Chip using Internal Scan Chains and Golomb Coding
Efficient Test Data Compression and Decompression for System-on-a-Chip using Internal Scan Chains and Golomb Coding Anshuman Chandra and Krishnendu Chakrabarty Department of Electrical and Computer Engineering
More informationTest-Wrapper Designs for the Detection of Signal-Integrity Faults on Core-External Interconnects of SoCs
Test-Wrapper Designs for the Detection of Signal-Integrity Faults on Core-External Interconnects of SoCs Qiang Xu and Yubin Zhang Computer Science and Engineering The Chinese University of Hong Kong Shatin,
More informationApproximating Computation and Data for Energy Efficiency
Approximating Computation and Data for Energy Efficiency Daniele Jahier Pagliari EDA Group Politecnico di Torino Torino, Italy 1st IWES September 20th, 2016, Pisa, Italy Outline Error Tolerance and Approximate
More informationLow Power Design Methods: Design Flows and Kits
JOINT ADVANCED STUDENT SCHOOL 2011, Moscow Low Power Design Methods: Design Flows and Kits Reported by Shushanik Karapetyan Synopsys Armenia Educational Department State Engineering University of Armenia
More informationImplementing Logic with the Embedded Array
Implementing Logic with the Embedded Array in FLEX 10K Devices May 2001, ver. 2.1 Product Information Bulletin 21 Introduction Altera s FLEX 10K devices are the first programmable logic devices (PLDs)
More informationMICROFLUIDICS lab-on-chip technology has made
250 IEEE TRANSACTIONS ON BIOMEDICAL CIRCUITS AND SYSTEMS, VOL. 4, NO. 4, AUGUST 2010 Digital Microfluidic Logic Gates and Their Application to Built-in Self-Test of Lab-on-Chip Yang Zhao, Student Member,
More informationHardware Implementation of Automatic Control Systems using FPGAs
Hardware Implementation of Automatic Control Systems using FPGAs Lecturer PhD Eng. Ionel BOSTAN Lecturer PhD Eng. Florin-Marian BÎRLEANU Romania Disclaimer: This presentation tries to show the current
More informationEnergy Efficient Scheduling Techniques For Real-Time Embedded Systems
Energy Efficient Scheduling Techniques For Real-Time Embedded Systems Rabi Mahapatra & Wei Zhao This work was done by Rajesh Prathipati as part of his MS Thesis here. The work has been update by Subrata
More informationInterconnect-Power Dissipation in a Microprocessor
4/2/2004 Interconnect-Power Dissipation in a Microprocessor N. Magen, A. Kolodny, U. Weiser, N. Shamir Intel corporation Technion - Israel Institute of Technology 4/2/2004 2 Interconnect-Power Definition
More informationDS1867 Dual Digital Potentiometer with EEPROM
Dual Digital Potentiometer with EEPROM www.dalsemi.com FEATURES Nonvolatile version of the popular DS1267 Low power consumption, quiet, pumpless design Operates from single 5V or ±5V supplies Two digitally
More informationSno Projects List IEEE. High - Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations
Sno Projects List IEEE 1 High - Throughput Finite Field Multipliers Using Redundant Basis For FPGA And ASIC Implementations 2 A Generalized Algorithm And Reconfigurable Architecture For Efficient And Scalable
More informationLeading by design: Q&A with Dr. Raghuram Tupuri, AMD Chris Hall, DigiTimes.com, Taipei [Monday 12 December 2005]
Leading by design: Q&A with Dr. Raghuram Tupuri, AMD Chris Hall, DigiTimes.com, Taipei [Monday 12 December 2005] AMD s drive to 64-bit processors surprised everyone with its speed, even as detractors commented
More informationLow Power Design for Systems on a Chip. Tutorial Outline
Low Power Design for Systems on a Chip Mary Jane Irwin Dept of CSE Penn State University (www.cse.psu.edu/~mji) Low Power Design for SoCs ASIC Tutorial Intro.1 Tutorial Outline Introduction and motivation
More informationUNIT-II LOW POWER VLSI DESIGN APPROACHES
UNIT-II LOW POWER VLSI DESIGN APPROACHES Low power Design through Voltage Scaling: The switching power dissipation in CMOS digital integrated circuits is a strong function of the power supply voltage.
More informationClass Project: Low power Design of Electronic Circuits (ELEC 6970) 1
Power Minimization using Voltage reduction and Parallel Processing Sudheer Vemula Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL. Goal of the project:- To reduce the power consumed
More informationScheduling and Communication Synthesis for Distributed Real-Time Systems
Scheduling and Communication Synthesis for Distributed Real-Time Systems Department of Computer and Information Science Linköpings universitet 1 of 30 Outline Motivation System Model and Architecture Scheduling
More informationVery Large Scale Integration (VLSI)
Very Large Scale Integration (VLSI) Lecture 6 Dr. Ahmed H. Madian Ah_madian@hotmail.com Dr. Ahmed H. Madian-VLSI 1 Contents Array subsystems Gate arrays technology Sea-of-gates Standard cell Macrocell
More informationDS1802 Dual Audio Taper Potentiometer With Pushbutton Control
www.dalsemi.com FEATURES Ultra-low power consumption Operates from 3V or 5V supplies Two digitally controlled, 65-position potentiometers including mute Logarithmic resistive characteristics (1 db per
More informationEE382V-ICS: System-on-a-Chip (SoC) Design
EE38V-CS: System-on-a-Chip (SoC) Design Hardware Synthesis and Architectures Source: D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design: Modeling, Synthesis, Verification, Chapter 6:
More information