First Name: Last Name: Lab Cover Page. Teaching Assistant to whom you are submitting

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1 Student Information First Name School of Computer Science Faculty of Engineering and Computer Science Last Name Student ID Number Lab Cover Page Please complete all (empty) fields: Course Name: DIGITAL SYSTEMS 1 Course Number: CIS3120 Section Number: Lab Date and Time: Teaching Assistant to whom you are submitting First Name: Last Name: Mark Assigned: Notes This (complete) lab exercise should be printed and stapled before coming to lab. Any questions requiring a written answer should be answered by writing in the spaces provided in this lab document, and the document should be submitted for marking. Remember to keep this document for study purposes. Also, you will need the signed version of this document if a re-grade or grade correction is requested. 1

2 School of Computer Science Digital Systems (CIS3120) Purpose To design a complete digital system with correctly functioning datapath and controller. A Sequential Multiplier In this final lab exercise you will use your knowledge of both combinational and sequential circuits to construct a 4-bit sequential multiplier circuit. A sequential multiplier circuit computes the product of two binary numbers in steps, much as we would if we were to do the multiplication with pencil and paper. Our sequential multiplier will take approximately 4 clock cycles to compute a product, but each cycle can be relatively short, as we only need to do one 8- bit addition and a shift of our multiplier. Problem Specification You are asked to design a 4 x 4-bit multiplier. The two 4-bit inputs, the multiplier and multiplicand, will already be loaded into two registers by other logic. Your multiplier is to compute the 8-bit product within approximately 4 clock cycles and leave the result in another register where it should stay until the next multiply operation. A description of the algorithm you are to implement is given in Fig. 1. Understanding the Specification Let s begin by clearing up two issues. First, you should assume that you are dealing with unsigned binary values. Second, you should assume that other logic will generate the load signals (Load1 and Load2) that will get the two 4-bit numbers into two registers. Finally, a start signal will be generated to initiate the 4-step multiplication. The result will end up in a separate 8-bit register 4 cycles later. Figure 2 shows a block diagram of the multiplier s data path and controller. Note that the controller has two inputs (besides the clock signal, clk) and three outputs. The inputs are the Start signal and the value of the rightmost (least significant) binary Digit of the multiplier value. The outputs are a signal to Clear the 8-bit accumulator register, a Load3 signal to load the same register, and a Shift signal to shift the multiplier value one bit to the right and a shift signal to shift the multiplier value one bit to the right (divide by 2). There are three registers for the multiplier, multiplicand, and product. The multiplier and multiplicand registers are loaded from two independent sets of 4 data wires, with 2

3 an additional 4 set to zero for the multiplicand register. Of course, there is also an 8-bit adder to perform the additions of the partial products. Product = 0 For i = 0 to 3 do If Multiplier[0] = 1 then Product = Product + Multiplicand Shift right the Multiplier Shift left the Multiplicand Figure 1: Behavioral Description of Multiplication Algorithm Multiplicand Multiplier 0 Load1 Digit Load2 Shift Clock Start Control Digit 8 8 Adder 8 Product 8 Clear Load3 Shif t Clear Load3 Figure 2: Sequential multiplier block diagram. 3

4 Implementation Since we must be able to shift the multiplier value to the right for each of the 4 clock cycles, the multiplier register must also implement a right shift in addition to the load capability. The multiplicand register is extended with an extra 4-bits initially loaded with zeroes. This is so that we can multiply-by-2 via a left shift of the multiplicand register and generate the partial product we need to accumulate. Thus, the multiplicand register is very similar to the multiplier registers except it has to shift left rather than right (with zeroes filling in from the right rather than from the left as in the multiplier register) and is twice the size. Note: You already constructed these registers in lab number 9. The accumulator is a simple 8-bit adder that could be designed using any of the techniques that we learned in class for creating fast arithmetic circuits. However, you should simply extend the 4-bit ripple-carry adder that you designed in lab four to 8 bits. The accumulator adds the contents of the product and multiplicand registers and makes the sum available at the input of the product register. The overall operation of the sequential multiplier is straightforward. For four cycles, the controller will look at a bit of the multiplier register and if it is 0, will do nothing as the partial product is 0, and if it is 1, it will add the multiplicand to the partial product and put the result in the product register. The multiplicand will have been shifted left one bit at a time in each cycle so as to adjust the value of the multiplicand to correspond to the position of the bit of the multiplier currently being used. At every clock edge the following actions take place in parallel. The multiplier shifts one bit to the right (dividing the multiplier by 2) so that its next bit can be observed. The multiplicand is shifted one bit to the left (multiplying the multiplicand by 2) so that it can be added conditionally to the parallel product through the accumulator adder. The accumulator adder adds the current multiplicand to the parallel product from the product register. The product register loads the next accumulated partial product. Because these actions happen in parallel, the product register loads the addition result prior to the multiplicand s shift. Figure 3 shows a state diagram for the controller. Notice that in reality the multiplier takes 5 cycles to compute a result as it uses the first cycle to clear the product register when it first receives a start signal. Clear is asserted as soon as Start is and is able to have the clearing effect on the product register on the same clock edge that takes the FSM into state S0. In each of the states S0 through S4, the FSM observes the value of the low-order multiplier digit and based on that value either loads and shifts (the multiplier and multiplicand registers right and left, respectively) or it simply shifts. The load and shift happens at the next clock edge so that by the time the FMS returns to the idle state it has observed all four bits of the multiplier and performed up to 4 partial product updates (depending on the number of bits that were equal to 1 in the multiplier register). 4

5 idle S0 Start Start/Clear,Load3,Load3 S1 S2,Load3,Load3 S3 Figure 3: Sequential multiplier controller state diagram. Your task is to implement the 4 x 4-bit sequential multiplier circuit as described above. It is recommended that prior to implementing the circuit you perform some sample calculations by hand to familiarize yourself with the algorithm itself. Then begin by first constructing the datapath and verifying that it works correctly. Input signals to the datapath can be generated using switches; output signals can be observed using binary probes. Once you are sure that the datapath is working as it should, implement the controller. You should use D-type flip-flops in 5

6 the construction of the controller, as these are the easiest to work with. Also, you should include an asynchronous reset so that the controller can be manually forced into a valid starting state. Once you have verified the correct operation of the controller, combine the datapath and controller together by making the appropriate input-output connections. Verify that your design is working correctly. Note: To test the correctness of your final circuit, you will find it easiest to generate appropriate waveforms in LogicWork s timing window. (Don t forget to add a clock to your design.) Once the calculation is complete, you can scroll back over these waveforms to verify that the circuit is functioning as it should. 6