ENGG1015: lab 3. Sequential Logic

Transcription

1 ENGG1015: lab 3 Sequential Logic 1 st Semester This lab explores the world of sequential logic design. By the end of this lab, you will have implemented a working prototype of a Ball ounter that you will use in the project. 1 Finding your lab partner You will be working with a randomly assigned partner for this lab. To find your assigned lab partner and the assigned table, 1. Log in to Moodle. 2. Select the assignment Lab 3 Partner Please proceed to your assigned table. 2 Getting the Files ownload the files for this lab from 3 Getting the Basic Right lock & Flip-Flop We will start with a simple circuit to experiment with the behavior of sequential circuit. 3.1 In Logisim, construct the following circuit: a b c d clk Figure 1: Simple sequential circuit You can find symbols of -flip-flop (FF) from the Memory library. The symbol of a -flip-flop in Logisim is shown in Figure 2. Note that the symbol is different from the one in lecture notes and from the Xilinx ISE tools. In Logisim, the input to the FF is labeled in the bottom left corner of the symbol. The output is located in top right corner of the symbol. Figure 2: -Flip-Flop in Logisim

2 You should connect the clock signal clk to the clock input located in top left corner of the symbol of all FFs. Instead of using a simple Pin as input, use a lock symbol instead. You can find the clock symbol under the Wiring library. 3.2 heck Yourself Test the behavior of the circuit using the Poke tool. You can toggle the value of a clock input similar to the way you toggle the value of a pin. If you toggle the value of an input to a FF when the value of clk is 0, does the value at the output change? What if the value of clk is 1? When does the output of a FF toggle? 3.3 Timing iagram omplete the following timing diagram of the above circuit given. a b c d clk 3.4 heckoff 1 Show to your TA the completed timing diagram of Figure 1. If the value of d is 1 in cycle n, what is the value of a in cycle n 3? What is the function of this circuit? 4 Ball ounting... Simple As 1, 2, 3 Here will build a logic circuit that counts the number of times a metal ball has passed through a detector. It stops counting when 3 balls have been detected, only after that will the circuit output a 1 on the done signal. The output should stay at 1 permanently until the state machine is reset. The digital logic control will be implemented in this lab, while the detection circuit will be built in next lab. 4.1 State Machine A simple way to implement the function of counting is to build a state machine that memorizes the number of balls it has detected so far. We will use a state machine with 4 states, namely Seen0, Seen1, Seen2, Seen3, which memorizes the fact that we have detected 0, 1, 2, and 3 balls respectively. At reset, the system should be in state Seen0. Page 2 of 5

3 The machine has 1 input signal, det, that is 1 if a ball is detected, 0 otherwise. It has 1 output signal, done, that is 1 only after 3 balls have been detected. In the following space, draw the state transition diagram of this ball counting machine. Make sure your state machine is a complete state machine all the necessary transition arcs must be included. 4.2 heck Yourself State Encoding We will encode the states using a simple binary scheme as follows: Encoding State s1 s0 Seen0 0 0 Seen1 0 1 Seen2 1 0 Seen3 1 1 How many states are there in our state machine? How many -flip-flops are needed to encode the states? 4.3 Next State Logic The next state logic is a combinational function that determines the state that a state machine should be at after the next clock tick. From a state transition diagram, the next state logic for a particular state can be obtained by enumerating the conditions of all the arcs entering that state. We denote the two bit next state signal as ns1 and ns0. omplete the following truth table of the next state logic of our state machine:

4 s1 s0 det ns1 ns Output Logic The output signal done should be 1 only after 3 balls have been detected. Write down the logic equation for done. done = 4.5 omplete State Machine You are now ready to implement the entire state machine. In Logisim, open the design cnt3.circ. Use the above results and the skills you have developed in the past few labs, implement the complete state machine by implementing the next state logic, the output logic, as well as the FFs that store the states. Some of the connections have already been implemented for you. In Logisim, you can use a Tunnel to connect signals in the circuit by its name instead of drawing long wires. To connect two signals in Logisim without drawing a wire between them, simply connect each of them to a tunnel. Then, label the tunnel with the same signal name in the setting pane. 4.6 heckoff 2 emonstrate your completed state machine to your TA and answer the following questions. Where are the states of the machine stored at? How will your circuit be different if a different encoding of the states were used? Which state does your machine start in? How is that accomplished in the real circuit? Is there any requirement in the state encoding to ensure this behavior? What if we want to count to 5 balls? How many states do we need? How many bits do we need if we use a binary encoding? Page 4 of 5

5 5 Getting to the board At the end of the semester, you need to incorporate the ball counting function to the project using the Basys2 board. Here, we will start the implementation work based on the previous results. 5.1 Open the file lab3.xise using Xilinx Project Navigator. ouble-click to open cnt3.sch from the esign pane. A display module is already placed in the design for your convenience. The current state (s1, s0) are connected to the display so you know which state you are at. Also, a ball detection module called detector has been added to your design. It takes the din input and output the det signal when a ball is detected. Use this det signal as an input to your state machine. 5.2 Implement the same design you had in Logisim above using the Xilinx ISE tools. To insert a -flip-flop, select the Flip Flop ategories and use the symbol fdc. (There are many similar variations of FF in that category, make sure you use fdc in this part of the lab.) For fdc, is input port, is output. lock input is labeled with a wedge in the pin. Finally, the pin clr is the clear signal. When clr is 1, it clears the content of the flip-flop to it s default value of 0 regardless of the value of the clock input. HINT : There are 3-input gates available in the Xilinx ISE tools, under the Logic category. NOT gates are listed as inv (Inverter). However, a better solution is to use the built-in symbols with inverted input. For example, the symbol and2b1 is a 2-input AN gate with 1 of the input inverted already. It saves time in constructing your circuit. Make sure you use the following naming convention for your signals to ensure correct connection in the.ucf file and to the rest of the design. name Signal din Input from the ball detection circuit. It is connected to button 3 in this lab. det Signal that indicates detection of a ball by processing din. done output signal that indicates 3 balls have been detected. onnected to led7 s1, s0 current state. ns1, ns0 next state. clr clear the states. onnected to button 0. clk clock input You do not need to create any I/O port in the design, they are all created for you already. To connect two points in the design, apart from drawing a physical wire, you can simply name the two nets with the same name. To give a name to a net, click the Add Net Name button, then on the Add Net Name Options pane, type the name in the Name field. Finally click on the net that you want to set the name. i.e., there is no need to use a tunnel as in Logisim to connect two nets in ISE. 5.3 heckoff 3 emonstrate to your TA a complete working ball counting machine on the Basys2 board. to your partners the design files. You may need them for your final project. Page 5 of 5