CHAPTER 5 DESIGNS AND ANALYSIS OF SINGLE ELECTRON TECHNOLOGY BASED MEMORY UNITS

Transcription

1 208 CHAPTER 5 DESIGNS AND ANALYSIS OF SINGLE ELECTRON TECHNOLOGY BASED MEMORY UNITS 5.1 INTRODUCTION The objective of this chapter is to design and verify the single electron technology based memory circuits and its application in memory devices. The memory for the computing system is a very important one; it should be smaller in size and easy to access. The present memories based on conventional technology, consume more power for storing small amount of data. Hence it is essential to design a memory, which is smaller in size but, has fast access time and consumes less power. These features can be achieved by single electron transistor, ( Korotkov 1999) and ( Katayama et al 1999) which is very attractive for multiple valued logic and threshold logic memories compared to CMOS devices( Guo et al 1997) and ( Banerjee et al 2003). In this chapter, the VC-SEEL based flip flops have been designed and discussed. A reconfigurable memory to realize all the memory logic using a single circuit has also been discussed. The single electron transistors are very much suitable for multiple valued logic (MVL) (Mahapatra et al 2005). Since the discrete number of electrons in the SET island can be directly related to MVL levels, this facilitates more states for a location. The inverter is used as a logic gate to construct a Multiple-valued logic memory element. Reconfigurable MVL- SET based memory elements have been also designed and the performances

2 209 of these devices are discussed. Further, the Spin SET based memory elements have been designed and discussed. The various shift register configuration using all the above methods have been simulated and performances are compared to verify the logic. Note that in this chapter, if not specified otherwise the X-axis and Y axis of figures are Time(s) and voltage (V) respectively. 5.2 SEB -THRESHOLD LOGIC GATE BASED RECONFIGURABLE FLIP FLOP The basic unit of storage is called as flip flop and it is the simplest kind of sequential circuit having two states either 1 or 0. Flip flops are two state sequential circuits that flip from one state to another and flop back. The state of a flip flop is the value that it currently stores. The stored value can be changed only at certain times determined by a clock input and the new value may further depend on the flip flop s current state and its control inputs. A digital circuit that contains flip flops is called a sequential circuit because its output at any time depends not only on its current input, but also on the past sequence of inputs that have been applied to it. In other words, a sequential circuit has memory of past events (Karafyllidis 2002). The threshold logic memory element designed by (Lageweg et al 2004) is used as basic element for realizing the reconfigurable flip flop. The memory like RS Latch, D Flip Flop, T flip flop and JK Flip Flop logics are evolved from the single reconfigurable flip flop element. This kind of memory elements is very much essential for reprogrammable devices and reprogrammable computing. The scheme for threshold logic reconfigurable flip flop is shown in Figure 5.1. It consists of two threshold logic gates(tlg 1,TLG 2) and three

3 210 static inverting buffers(inv 1,INV 2,INV 3). The threshold equations (5.1) and (5.2) for the reconfigurable flip flop are derived by considering the weigtage and threshold levels of all the logics of flip flops. Based on the threshold levels the various circuit parameters are determined as per the design procedure of SEB gate desin discussed in the second chapter. TLG 1= sgn {2X(S, J, D) Y(R, K) -Q t } (5.1) TLG2 = sgn{tlg1 TLG1 + Q t} (5.2) The threshold gates derived from the generic threshold gate scheme require an output buffer for correct operation in a network structure. It consists of two threshold gates and three inverters. The two inverters in series connected at the output terminals are arranged such that both Q and its logic complement QN are available. The threshold logic gates based implementation has the additional advantage that it does not have a forbidden input combination. Figure 5.1 Threshold based reconfigurable flip flop The inputs of the flipflop are applied to TLG 1. The inputs capacitances of TLG 1 is properly weighed,so that it can be configured for various flip flops logics. The TLG 2 gets three inputs such as output of TLG

4 211 1,inverted output of TLG 1 and previous output Q. Finally two inverters INV 2,INV 3 are used to produce output Qn,output Q respectively. The clock input is applied at the sourse terminals of Ptype devices of INV 2 and INV 3.The Single electron transistor based reconfigurable flip flop circuit is shown in Figure 5.2. In the following section the working principle of various flipflops like SR,D,JK and T are explained and their simulation results are discussed. Figure 5.2 SEB threshold logic based reconfigurable flip flop RS flip flop The R-S flip flop logic takes two inputs, namely RESET (R) and SET (S), and two outputs Q and Q bar. The two outputs are complement to each other. The three inputs X(S), Y(R) and Q t (feedback output) with weightage of 2,-1, 1 respectively are supplied to the TLG1. The input capacitance of X is comparatively high. The threshold equations of the reconfigurable flip flops are modified for RS flip flop as given in equations (5.3) and (5.4).

5 212 TLG1 = sgn{2x(s) Y(R) Q t} (5.3) TLG2 = sgn{tlg1 TLG1 + Q t} (5.4) The output of the SEEL threshold logic gate TLG 2 is given as input to static inverting buffer. This can produce output Q n. This Q n is given as input to another static inverting buffer for getting output Q t+1. The inverting buffer s Vbias is driven by the single clock input. The simulation result of RS flip flop is shown in Figure 5.3.When the inputs are S = 0, R = 0 and clk= 1 then the outputs are Q t+1 = 0 and Q n = 1 when the input S becomes 1, R = 0 and clk= 1 the outputs are set to Q t+1 = 1 and Q n = 0. These output values are memorized when S returns to 0. Likewise, when R becomes 1, S = 0, clk= 1 the outputs are reset to Q t+1 = 0 and Q n = 1, which is memorized when R returns to 0. Next, R and S are both set to 1, as a result of which the outputs Q t+1 and Q n remain unchanged as this input combination. Likewise, when R and S are simultaneously set to 0, the output also remains unchanged. The output response shows that the circuit correctly implements the behavior of the R-S flip flop. Voltage (V) Time (s) Figure 5.3 Simulation result of reconfigurable flip flop for RS FF logic

6 213 D flip flop The D flip flop logic is realized by configuring the TLG 1 which takes two inputs X(D) and Q t (feedback output) weighted 2, 1 respectively. The threshold logic equation for D flip flop are derived by modifying the equations (5.1 ) and (5.2) as given in equations (5.5) and (5.6). TLG1 = sgn{2x(d) Q t} (5.5) TLG2 = sgn{tlg1 TLG1 + Q t} (5.6) The simulation result of D flip flop is shown in Figure 5.4.When the input is D = 0, and clk= 1 then the outputs are Q t+1 = 0 and Q n = 1 when the input D becomes 1, and clk= 1 the outputs are set to Q t+1 = 1 and Q n = 0. These output values are memorized when D returns to 0. When clk= 0 the output Q t+1 follows the previous output Q t. We therefore conclude that the circuit correctly implements the behavior of the D flip flop. Voltage (V) Time (s) Figure 5.4 Simulation result of reconfigurable flip flop for D FF logic

7 214 JK flip flop The JK flip flop logic is realized by configuring the reconfigurable structure. The TLG takes the three inputs X(J), Y(K) and Q t (feedback output) weighted 2, -1, 1 respectively. The threshold logic equation for JK flip flop are given in equations (5.7) and (5.8). TLG1 = sgn{2x(j) Y(K) + Q t} (5.7) TLG2 = sgn{tlg1 TLG1 + Q t} (5.8) The simulation result of JK flip flop is shown in Figure 5.5. When the inputs are J = 0, K = 0 and clk= 1 then the outputs Q t+1 depends on the previous value of Q t. When the input J becomes 1, K = 0 and clk= 1 the outputs are set to Q t+1 = 1 and Q n = 0. These output values are memorized when J returns to 0. Likewise, when K becomes 1, J = 0, clk= 1 the outputs are reset to Q t+1 = 0 and Q n = 1, which is memorized when K returns to 0. Next, J and K are both set to 1, as a result of which the outputs Q t+1 and Q n are toggle with each clock pulse. Likewise, when J and K are simultaneously set to 0, the output also remains unchanged. We therefore conclude that the circuit correctly implements the behavior of the JK flip flop. Voltage (V) Time (s) Figure 5.5 Simulation result of reconfigurable flip flop for JK FF logic

8 215 T Flip flop The reconfigurable flip flop configured as Toggle flip flop as follow, the TLG 1 takes the three inputs X(T), Y(T) and Q t (feedback output) and weighted 2, -1, 1 respectively. The threshold equation for T flip flop are given in equations (5.9) and (5.10). TLG1 = sgn{2x(j) Y(K) + Q t} (5.9) TLG2 = sgn{tlg1 TLG1 + Q t} (5.10) The simulation result of T flip flop is shown in Figure 5.6. When the input X(T) andy(t) both are set to high the Toggling of the output takes place. If clk= 1 then the output Q t+1 toggles from low to high and high to low. If clk= 0 then the output Q t+1 depends on the previous value of Q t. Voltage (V) Time (s) Figure 5.6 Simulation result of reconfigurable flip flop for T FF logic The performance measures of reconfigurable flip flop are estimated in terms of area, delay and energy consumption and summarized in Table 5.1. The delay time and energy are estimated based on the switching pattern of each flip flop logic. It is estimated that the SR flip flop logic consumes more

9 216 energy but with less delay compared to the the other flip flop logic.the J-K and T flip flops consumes less energy but the delay time is slightly higher than that of the other flip flops logic. Table 5.1 Performance measures of reconfigurable flip flops Logic Area (No. of elements) Delay time Switching energy SR flip flop ns meV D flip flop ns meV JK flip flop ns meV T flip flop ns meV 5.3 VC-SEEL BASED FLIP FLOP AND MEMORY DEVICES The simulation of VC-SEEL based the various flip flop and the shift register are discussed in the following section VC-SEEL Based Flip Flop The proposed VC-SEEL based memory elements are realized in SET technology. Types of flip flops are designed with the threshold equations and are implemented in the single electron box. RS flip flop The threshold equation for the RS flip flop is derived by considering the weigtage and threshold levels of flip flops.the threshold equation of RS flip flop with the inputs R and S and previous state Q is given by equation (5.11)

10 217 Q* = sgn{ - R + S + Q - 1} (5.11) The threshold logic of RS flip flop is pictorially shown in Figure 5.7, with inputs S and R and the outputs Q and Q bar. The * in Q* represents the next state of Q. S R Q* o o Q bar Figure 5.7 Threshold diagram of RS flip flop The various circuit parameters of RS flip flop are determined as per the design procedure of SEB gate desin discussed in the second chapter in accordance with the threshold logic equation of the the RS flip flop. The designed parameters of RS flip flop are as follows. C + 1(w=+1) = C + 2(w = 1) =C - 1(w = -1) = 0.5aF; C out = 9.5aF, C bias = 0.5aF, V bias = V. For inverter circuit 1 we use C - 1(w = -1) = 0.5aF, C bias = 0.5aF, C out = 9.5aF, V bias = V, Rj =105ohm, Cj = 0.01aF. For invertor circuit 2 we use C - 1(w = -1) = 0.125aF, C bias = 0.5aF, C out = 9.3aF, V bias = V, R j = 10 5 Ω, Cj = 0.01aF. The circuit diagram of VC-SEEL based RS flip flop is shown in Figure 5.8 with one threshold function to realize the threshold equation of the RS flip flop. The inverter 1 and inverter 2 acts as a buffer circuit to retain the last value of Q for providing feedback to the threshold function of RS flip flop.

11 218 SR VC-SEEL gate VC-SEEL inverter Figure 5.8 VC-SEEL based RS flip flop The input variable shows logic 0 as 0V and logic 1 as 16mV. The simulation result of VC-SEEL based RS flip flop is shown in Figure 5.9. The output response of the flip flop shows that when S is high the output is set, i.e., high and when R is high, the output is reset, i.e., low. Clocked RS flip flop Synchronous circuits change their states only when clock pulses are present. The operation of the basic RS flip flop can be modified by providing an additional control input that determines when the state of the flip flop is to be changed. The threshold equation of clocked RS flip flop is given by equation (5.12) ( Durrani et al 2000).

12 219 Q* = sgn{ 2 clk - R + S + Q - 3} (5.12) The threshold logic diagram of clocked R-S flip flop with three inputs S, R and clk and the outputs are Q and Q bar is depicted in Figure S input Voltage(V) R input Q output Q_bar output Time (S) Figure 5.9 Response of the VC-SEEL based RS flip flop S R o o Q Q bar Clk Figure 5.10 Threshold diagram of clocked RS flip flop

13 220 The designed parameters of clocked RS flip flop are as follows. C + 1(w=+1) = C + 2(w = 1) =C - 1(w = -1) = 0.5aF; C + 3(w = 2) = 1aF, C out = 9.5aF, C bias = 0.5aF, V bias = V. For invertor circuit 1 we use C - 1(w = -1) = 0.5aF, C bias = 0.5aF, C out = 9.5aF, V bias = V, Rj =105ohm, Cj = 0.01aF. For invertor circuit 2 we use C - 1(w = -1) = 0.125aF, C bias = 0.5aF, C out = 9.3aF, V bias = V, R j = 10 5 Ω, Cj = 0.01aF. The circuit diagram of clocked RS flip flop using VC-SEEL approach is shown in Figure 5.11, with one threshold function to realize the threshold equation of the clocked RS flip flop. The inverter 1 and inverter 2 acts as a buffer circuit to retain the last value of Q for providing feedback to the threshold function of RS flip flop. Clocked RS gate inverter Figure 5.11 VC-SEEL based clocked RS flip flop

14 221 The input variable shows logic 0 as 0V and logic 1 as 16mV. The clocked RS flip flop is designed using proposed VC-SEEL and the simulation result is shown in Figure 5.12 (a) and 5.12 (b). The response shows that when S is high the output is set, i.e., high and when R is high, the output is reset, i.e., low. Clock input Voltage (V) Time (s) Voltage (V) S input Time (s) Voltage (V) R input Time (s) (a) RS flip flop input clock, R and S signals Figure 5.12 Response of the VC-SEEL based clocked RS flip flop

15 222 Q output Time (s) Q bar output Voltage (V) Voltage (V) Time (s) (b) Output of clocked RS flip flop Figure 5.12 (Continued) The response of the clocked RS flip flop shows that, when the control input clock is not active, the output becomes low. If the clock is active, the clocked RS flip flop is enabled and the outputs are obtained as per its logic.

16 223 D flip flop The threshold equation for the D flip flop is derived by considering the weigtage and threshold levels of flip flop.the threshold equation of D flip flop with the inputs R and S and previous state Q is given by equation (5.13). Q* = sgn{ 2 clk Inv(D) + D + Q - 3} (5.13) The threshold logic diagram of D flip flop is depicted in Figure The designed parameters of clocked D flip flop are as follows. C + 1(w=+1) = C + 2(w = 1) =C - 1(w = -1) = 0.5aF; C + 3(w = 2) = 1aF, C out = 9.5aF, C bias = 0.5aF, V bias = V. For invertor circuit 1 : C - 1(w = -1) = 0.5aF, C bias = 0.5aF, C out = 9.5aF, V bias = V, Rj =105ohm, Cj = 0.01aF. For invertor circuit 2: C - 1(w = -1) = 0.125aF, C bias = 0.5aF, C out = 9.3aF, V bias = V, R j = 10 5 Ω, Cj = 0.01aF. D Inv D o o Q Q bar Clk Figure 5.13 D flip- flop threshold gate The circuit diagram of D flip flop using VC-SEEL approach is shown below in Figure 5.14 with one threshold function to realize D flip flop from the threshold equation of the clocked RS flip flop. The inverter 1 and inverter 2 act as a buffer circuit to retain the last value of Q for providing feedback to the threshold function of D flip flop.

17 224 D logic gate VC-SEEL inverter Figure 5.14 VC-SEEL based D flip flop clock Time (s) input Voltage (V) Voltage (V) Time (s) (a) Input signal -D flip flop Figure 5.15 Responses of the VC- SEEL based D flip flop

18 225 Q output Time (s) Q bar output Voltage (V) Voltage (V) Time (s) (b) Output response of D flip flop. Figure 5.15 (Continued) The input variable shows logic 0 as 0V and logic 1 as 16mV. The D flip flop is designed using proposed VC-SEEL and the simulation result is shown in Figure 5.15 (a) and 5.15(b). It shows that when S is high the output is set, i.e., high and when R is high, the output is reset, i.e., low. Positive edge triggered D flip flop A positive-edge-triggered D flip flop combines a pair of D latches as shown in Figure 5.16, to create a circuit that samples its D input and

19 226 changes its Q and Q bar outputs only at the falling edge of a controlling clock signal. The first latch is called master; it is open and follows the input when clock is low. When clock goes high, the master latch is closed and its output is transferred to the second latch called as slave. The slave latch is open all the while that clock is high, but changes only at the beginning of this interval, because the master is closed and unchanging during the rest of the interval. The truth table of the positive edge triggered D flip flop is shown in the Table 5.2. below. The block diagram of positive-edge-triggered D flip flop is shown Figure 5.16 Block diagram of positive edge-triggered D flip flop The design equation of the master flip flop is given as Q* = clk bar D + clk Q (5.14) The equation (5.14) does not satisfy the properties of the threshold function to be implemented in one SEB, so it is required to implement with two SEBs.

20 227 Table 5.2 Truth table of positive edge-triggered D flip flop D CLK Q* Q bar 0 Rising edge (0 to 1) Rising edge(0 to 1) 1 0 X 0 Last Q Last Q bar X 1 Last Q Last Q bar A = D clk -1 (5.15) Q* = 2A clk Q +1 (5.16) The design equation (5.17) of the slave flip flop is given as Q* = clk D + clk bar Q (5.17) The above equation (5.17) does not satisfy the properties of the threshold function to be implemented in one SEB, so it is required to implement with two SEBs as given in equations (5.18) and (5.19). These threshold equations are used for implementing the Positive edge triggered D flip flop using VC-SEEL technique. The circuit diagram for positive edgetriggered D-flip flop is shown in Figure 5.17, its input and corresponding output response are shown in Figures 5.18(a) and 5.18(b). A = -D clk +1 (5.18) Q* = -2A +clk Q (5.19)

21 228 Figure 5.17 VC-SEEL based positive edge-triggered D flip flop Voltage (V) Voltage (V) Time (s) (a) data input Time (s) (b) clock input Voltage (V) Time (s) (c) Output response of D flip flop Figure 5.18 Response of VC-SEEL based edge-triggered D flip flop

22 229 Comparison of VC-SEEL based memory elements The performances of the VC-SEEL based memory elements like RS flip flop, Clocked RS flip flop, D flip flop, and Positive triggered D flip flop based on the parameters like area, delay, power consumption and speed power product are measured and summarized in Table 5.3, it reveals that the memory circuits based on VC-SEEL requires less elements, reduction in delay and consumes less energy. Table 5.3 Comparison of VC-SEEL based flip flops Parameter RS flip flop Clocked RS flip flop D flip flop edge triggered D flip flop Area 15 elements 16 elements 20 elements 39 elements Propagation delay Energy consumption Speed-power product ns ns ns ns mev mev mev mev pj pj pj pJ VC- SEEL Based Shift Registers The VC-SEEL based four bit shift registers such as parallel in parallel out, parallel in serial out, serial in serial out, serial in parallel out operations have been simulated and discussed in the following section. The registers are realized with the voltage controlled SEEL based D-FF. Due to SET s circuit size complexity only the block diagrams are shown here. The study based on simulation show that the VC-SEEL based D-FF function exactly.

23 230 PARELLEL - IN PARELLEL OUT The A parallel-in/parallel-out shift register combines the function of the parallel-in, serial-out shift register with the function of the serial-in, parallel-out shift register to yield the universal shift register. The block diagram and signal flow is shown in Figure The clock signal is given synchronously to all the flip flops. Each and every D Flip flops are operated as explained above in section The data presented at D 3 through D 0 are loaded into the registers in parallel. This data at Q 3 through Q 0 are shifted by the number of pulses presented at the clock input. The shifted data is available at Q 3 through Q 0. The clk, inputs (D0,D1,D2,D3) and outputs (Q1,Q2,Q3,Q4) are shown in Figure 5.20, for the first clock rise the input D0,D1,D3 are high and D2 is low, this data is maintained and outputted till the second clock occurs, similarly for all the subsequent clocking the register functions properly and output the data in parallel. Figure 5.19 Block diagram of PIPO shift register

24 231 (a) Clock signal PIPO shift register (b) Data D3 (c) Output Q3 (d) Data D2 (e) Output Q2 (f) Data D1 (g) Output Q1 (h) Data D0 (i) Output Q0 Figure 5.20 Simulation results of VC-SEEL based PIPO shift register

25 232 PARELLEL IN SERIAL - OUT Figure 5.21 Block diagram of PISO shift register The 4-bit PISO shift register is constructed by connecting four D FF as shown in Figure The clock signal is given synchronously to all the flip flops. Data is loaded into all stages at once of a parallel-in/serial-out shift register. The data is then shifted out via "data out" by clock pulses. Since a (a) input Clock (b) Input D0 (c) input D1 (d) Input D2 (e) input D3 (f) Output Figure 5.22 Simulation Results of VC-SEEL based PISO shift register

26 stage shift register is considered, four clock pulses are required to shift out all the data. The responses are shown in Figure 5.22 The FF3 data presents at the "data out" up until the first clock pulse; FF2 data appears at "data out" between the first clock and the second clock pulse; FF1 data presents between the second clock and the third clock; and FF0 data presents between the third and the fourth clock. After the fourth clock pulse and thereafter, successive bits of "data in appears at "data out" of the shift register after a delay of four clock pulses. SERIAL IN SERIAL OUT The serial in serial out shift register is shown in Figure The data at the input will be delayed by four clock periods from the input to the output of the shift register. The clock signal is given synchronously to all the D flip flops. Figure 5.23 Block diagram of SISO shift register The responses of the SISO is shown in Figure The Data at "data in terminal (logic high), appears at the FF0 output after the first clock pulse. After the second pulse FF0 data is transferred to FF1 output and "data in" is transferred to FF0 output. After the third clock, FF2 is replaced by FF1;

27 234 FF1 is replaced by FF0; and FF0 is replaced by "data in". After the fourth clock, the data originally present at "data in" is at FF3, "output". The "first in" data is "first out" as it is shifted from "data in" to "data out". (a) Clock (b) input (c) Output Figure.5.24 Simulation Results of VC-SEEL based SISO shift register SERIAL - IN PARELLEL OUT Figure 5.25 Block diagram of SIPO shift register

28 235 The 4-bit SIPO shift register is shown in Figure The clock signal is given synchronously to all the flip flops. Four data bits will be shifted in from "data in" by four clock pulses and be available at Q0 through Q3. The response of the SIPO is shown in Figure 5.26 (a) 5.26 (g). After the first clock, the data at "data in terminal (high) appears at Q0. After the second clock, The old Q0 data appears at Q1; Q0 receives next data from "data in". After the third clock, Q1 data is at Q2. After the fourth clock, Q2 data is at Q3. (a) Clock (b) Clock bar (c) Input signal (d) Output Q0 (e) Output Q1 (f) Output Q2 (g) Output Q3 Figure 5.26 Simulation results of VC-SEEL based SIPO shift register

29 VC-SEEL Based Counters The counters are useful and important component of digital system, the following section explain the realization of counters using VC-SEEL. RING COUNTER Figure 5.27 Block diagram of ring counter If the serial output of a SISO register is connected to the serial of a shift input, data can be perpetually shifted around the ring as long as clock pulses are present. For example, the data pattern will repeat every four clock pulses. However, we must load a data pattern. The block diagram of the ring counter is shown in Figure The output response of the ring counter is shown in Figure 5.28 (a) 5.28 (f), the input is given to the FF3, when the clock pulse is present, the input data shifted to the next flip flops from left to right. The process repeats for the clocking operation.

30 237 (a) Input signal (b) output Q3 (c) Output Q2 (d) Output Q1 (e) Output Q0 (f) Input Clock signal Figure 5.28 Simulation results of VC-SEEL based ring counter JOHNSON COUNTER The switch-tail ring counter, also know as the Johnson counter, overcomes some of the limitations of the ring counter. Like a ring counter, a Johnson counter is a shift register fed back on its self. It requires half the stages of a comparable ring counter for a given division ratio. If the complement output of a ring counter is fed back to the input instead of the true output, a Johnson counter results. The schematic diagram of Johnson counter is shown in Figure 5.29.

31 238 Figure 5.29 Block diagram of Johnson counter This "reversed" feedback connection has a profound effect upon the behavior of the otherwise similar circuits. Re-circulating a single 1 around a ring counter divides the input clock by a factor equal to the number of stages. The Johnson counter is cleared with all stages to 0s before the first clock. The output responses are shown in Figure 5.30 (a) (f), the first clock shifts (a) Clock Signal (b) Clock bar signal (c) Input Signal (d) Output signal Q2 (e) Output signal Q1 (f) Output signal Q0 Figure 5.30 Simulation Results of VC-SEEL based Johnson counter

32 239 two 0s from (Q 2 Q 1 ) to the right into ( Q 1 Q 0 ). The 1 at Q 0 ' (the complement of Q) is shifted back into Q 2. Thus, we start shifting 1s to the right, replacing the 0s. Where a ring counter recirculated a single 1, the 3-stage Johnson counter recirculates three 0s then three 1s for a 6-bit pattern, then repeats. The VC-SEEL based memory elements have been discussed in this section. The results are verified by means of simulation. The performance measures are summarized in the Table 5.4. The next section discusses multiple valued memory circuits. Table 5.4 Performance measures of VC-SEEL based shift registers and counters Area Delay Switching energy PDP D flip flop ns mev pj Shift register/counter ns 1.66 mev 2.2 PJ 5.4 MULTIPLE VALUED LOGIC BASED MEMORY ELEMENTS AND DEVICES This section discuss the single electron transistor based multiple valued logic memory elements and devices. The SET circuits are very much suitable for multiple valued logic because of the discreteness of the electronic charge in the Coulomb Island and it can be directly related to multiple-valued operation. The basic functioning and logical operation have been discussed in chapter 3. The MVL requires very less number of devices for realizing the memory elements; this unique nature reduces the power consumption very drastically and the SET based MVL memory system ensures that the critical data is retained during changes in or loss of system power without much changes. This section discusses eight valued memory elements design.

33 Eight Valued Flip Flop The eight valued inverter has been designed and used as an element for realizing the memory devices. The design procedure of eight valued inverter is discussed in chapter 3. The stability diagrams for eight valued inverter is shown in Figure The plot is drawn between Vin and Vb1. The white region in the plot represents the stable region where the coulomb blockade occurs. The black region in the plot represents an unstable region where tunneling frequently occur. The unstable region is started at 20 mv and ended with 16mv. The ending point of unstable region from up to down determines the operating voltage, the operating voltage is taken as 16mv. Near to this the stable and unstable regions are overlapped, where the eight discrete triangle shaped white regions are achieved. The corresponding voltage available in Vin with respect to upper tip of the triangle is taken as one logic state, there are eight such eight logic states are available, this logic states are more stable in between tips of two black triangles. The stability plot clearly explains coulomb blockade bias condition for several internal states. The internal state of the circuit is given by (l, m, n), where l, m, and n are the number of electrons that can exist at islands L, M, and N, respectively. In (l, m, n) m mainly determines the output voltage, while l and n slightly modify the output voltage. If we increase the m value the output voltage is decreases. The eight internal states available from left to right having number of electrons as (0, 7, 0), (0, 6, 0), (0, 5, 0), (0, 4, 0), (0, 3, 0), (0, 2, 0), (0, 1, 0) and (0, 0, 0) respectively and are used to output multiple values 7,6,5,4,3,2,1 and 0, respectively for the corresponding input value (Vin). A multiple-valued inverter operation can be achieved by moving the bias point along the AB locus in Figure 5.33, because the bias point moves across eight stable regions with different m s, the transfer characteristics should look like a staircase. At the origin, more than two stable

34 241 regions overlapped, which makes the circuit multi-stable at the bias point D. This characteristic can be exploited to create an inverted multiple-valued memory function. If we move the bias point along the locus A B C D, the electron arrangement becomes (0, 4, 0) at B, and it can be maintained at point D. Therefore, the stored information can be maintained after Vdd and Vin are turned off. Hence this logic inverter can be used as a memory element. Vb1 (V) Vin (V) Figure 5.31 Stability diagram for eight valued inverter Table-5.5 MVL Logic states and their voltage levels Voltage Bit level Inverted Logic state (mv) representation logic

35 242 The voltage levels of each logic state is determined and tabulated in Table 5.5. This table also contains bit level representation and the inverted value of the corresponding logic states. The various circuit parameters of the eight valued inverters are estimated as per the design procedure discussed in the chapter3 and they are as follows: Cj1=1aF, Cj2 = 2aF, CG=2aF, C B = 3 af, C L = af. EIGHT VALUED D FLIP- FLOP Figure 5.32 Eight valued D flip flop Circuit The eight valued D flip flop circuit is shown in Figure 5.32, it consists of two identical eight valued inverters. It stores any one of the eight different logic states; the D Flip Flop circuit stores the input value at the edge of the clock pulse. The circuit is multi-stable on the input-voltage therefore it acts as a latch that maintains the output signal and ignores any input signal. The clock signal CLK is applied to node VB, and the inverted clock signal CLK is applied to node V A. For CLK = 0, the first inverter changes its state

36 243 depending on the value of Vin, but the second one does not. For CLK= 1, the first inverter s state is independent of the input signal, while the second one sets and maintains its output based on the signal received from the first one. As seen in Figure 5.33 (a) 5.33 (d), the input signal is stored when the clock voltage is high, and the stored value is maintained after the clock signal is turned off. The output response show that the D flip- flop capture the data during the every clocking and stores it till the next clock triggering. For instance, the input during the third clock is state 8, which is maintained constant till the next clock is occurred. Input Va1 (a) Input Signal (b) Input signal Va1 (c) Input Signal Vb1 (d) Output signal Figure 5.33 Simulation Results of eight valued D flip flop Eight Valued Shift Registers The terinary state shift registers are constructed by connecting eight valued D flip flops discussed in the previous section. Each stages of this register can store any one of eight different logic states mentioned in

37 Table 5.5. The operation of the all the shift registers are described in the section SERIAL - IN SERIAL OUT The simulation results are shown in Figure 5.34, the clock and inverter clock signals for the D flip flops are shown in Figures 5.34(a) and 5.34 (b). For the serial input sequence as seen in Figures 5.34(c) the exact serial output is generated as shown in Figures 5.34(d), during the first four clocking period the state 2,4,6,8 and 8 are inputted one by one and shifted serially for the sub sequent clocking. For the input state 6 the clocking remains off, this is exactly reflected in the output that the previous state 4 as the output. When the fourth clocking is applied the state 8 is maintained and that is also getting reflected at the output terminal. Va1 Vb1 (a) Input Signal va1 (b) Input signal Vb1 (c) Input Signal (d) Output signal Figure 5.34 Simulation results of eight valued SISO register

38 245 SERIAL - IN PARELLEL OUT The simulation results of eight valued Serial in parallel out shift register are shown in Figure 5.35 (a) 5.35 (g). The output at the first D flip flop of the register shows all the inputs are shifted serially and outputted in parallel, the Q0,Q1,Q2,Q3 show the parallel output response of the SIPO register. (a) Input Signal va1 (b) Input signal Vb1 (c) Serial Input (d) Output signal Q0 (e) Output signal Q1 (f) Output signal Q2 (g) Output signal Q3 Figure 5.35 Simulation results of eight valued SIPO register

39 246 PARELLEL - IN PARELLEL OUT The simulation results of eight valued parallel in parallel out shift register are shown in Figure 5.36 (a) 5.36 (j). The Va1 and Vb1 are clock (a) Input signal Va1 (b) input signal Vb1 (c) Data D3 (d) Output signal Q3 (e) Data D2 (f) Output signal Q2 (g) Data D1 (h) Output signal Q1 (i) Data D0 (j) Output signal Q0 Figure 5.36 Simulation results of eight valued PIPO register

40 247 and inverted clock applied at the inverters of the all the D flip flops. The D0,D1,D2 and D3 are the parallel input sequence and the corresponding shifted parallel output sequences are shown in Q0,Q1,Q2 andq3. PARELLEL IN SERIAL OUT The simulation results of eight valued parallel in serial out shift register are shown in Figure 5.37 (a) 5.37 (g). The Va1 and Vb1 are clock and inverted clock applied at the inverters of the all the D flip flops. (a) Input signal Va1 (b) input signal Vb1 (c) Data D0 (d) Data D1 (e) Data D2 (f) Data D3 (g) Ouput signal Figure 5.37 Simulation results eight valued PIPO register

41 248 The D0, D1, D2 and D3 are the parallel input sequence and the corresponding serial output sequence. For the first instant of the clock the output is the data D3 and the second clock outputs the D2, the third one outputs the D1 and D0 is getting shifted serially for the occurrence of the fourth clock Eight Valued Counters The terinary state counters are constructed by connecting eight valued D flip flops discussed in the previous section. Each stage of this counter can store any one of eight different logic states mentioned in Table 5.5. The operations of the counters are described in the section RING COUNTER The simulation results of eight valued ring counter are shown in Figure The Va1 and Vb1 are clock and inverted clock applied at the inverters of the all the D flip flops. The input sequence is shown in Figure 5.38 (c). The ring counter values are as seen in Figures 5.38(d)- 5.38(g). These responses show that for every clocking instant the counter value are obtained as per the ring counter logics. JOHNSON COUNTER The simulation results of eight valued Johnson counter are shown in Figure The Va1 and Vb1 are clock and inverted clock applied at the inverters of the all the D flip flops. The input sequence is shown in Figures 5.39(c). The Johnson counter values are as seen in Figures 5.39(d) (f). These responses show that for every clocking instant the counter value are obtained as per the Johnson counter logics.

42 249 (a) Input signal Va1 (b) input signal Vb1 (c) Input data (d) Output Q0 (e) Output Q1 (f) Output Q2 (g) Output Q3 Figure 5.38 Simulation Results eight valued ring counter

43 250 (a) Input signal Va1 (b) input signal Vb1 (c) Output Q2 (d) Output Q1 (e) Output Q0 Figure 5.39 Simulation results eight valued Johnson counter Table 5.6 Performance measures of eight valued memory devices Area Delay(s) Switching energy (W) PDP (J) Inverter x x x10-24 D flip flop x x x10-24 Shift register/counter x x x10-23 The results are verified by means of simulation and the performance measures of eight valued memory circuits are summarized in Table 5.6. The next section discusses the charging SET multiple valued memory circuits.

44 5.5 RECONFIGURABLE MVL-SET BASED MEMORY ELEMENTS AND DEVICES 251 This section discusses reconfigurable MVL- SET based memory elements. The advantage of this approach is reduced number of transistors. By controlling the bias voltage applied to the back gate, the Coulomb blockade conditions are adjusted to realize the configurable logics. The detailed design procedures of reconfigurable MVL- SET are discussed in the chapter 3. Figure 5.40 Reconfigurable MVL- SET inverter The reconfigurable MVL- SET based inverter circuit is shown in Figure It acts as an eight valued inverter as explained in chapter3. This circuit acts as a charging SET (PSET), when the inverting operation is taking place. Between the subsequent input data the SET device should be properly discharged by configuring it as NSET. The voltage at the gate capacitance Cg (i.e. input node) and the back gate capacitance Cb should be made high as maximum bias voltage. The input and the output responses of the reconfigurable MVL-SET are shown in Figure 5.41(a) 5.41 (d).

45 252 Vin Vdd (a) Vin signal (b) Vdd Vb Output (c) Vb signal (d) Output response Figure 5.41 Simulation results of reconfigurable MVL- SET based inverter Reconfigurable MVL-SET Based D Flip Flop The D Flip flop circuit stores the input value at the edge of the clock pulse. The reconfigurable MVL-SET based D flip flop is shown in Figure It consists of one reconfigurable MVL SET inverter and one Tucker type inverter, both are eight valued logic inverters. If the clock signal CLK is applied to node Va1, and the inverted clock signal CLK is applied to node V b1 and reset signal is applied simultaneously to node Vin and node Vc1 before each new input is applied at the gating terminals, in order to reset the previous values available in reconfigurable MVL SET inverter. For CLK = 0, the reconfigurable MVL SET inverter changes its state depending on the value of Vin, but the second one does not. For CLK= 1, the inverter s state is independent of the input signal, while the second one sets and maintains its output based on the signal received from the reconfigurable MVL SET inverter. After this process the output value is maintained in inverter2, till the next clock pulse.

46 253 Figure 5.42 Reconfigurable MVL-SET based D flip flop As seen in Figure 5.43(a) 5.43(e), the input signal is stored when the clock voltage is high and when the clock signal is turned off, the stored value is maintained till the reset signal applied to both the inverters. (a) Input signal Va1 (b) input signal Vb1 (c) input signal (d) Vc1 signal (e) Output response Figure 5.43 Simulation results of reconfigurable MVL-SET based D flip flop

47 Reconfigurable MVL-SET Based Shift Registers The terinary state shift registers based on reconfigurable MVL-SET logics are constructed by connecting eight valued D flip flops discussed in the previous section. The each stages of this register can store any one of eight different logic states mentioned in Table 5.5. The operation of the all the shift registers are described in the section SERIAL - IN SERIAL OUT The serial in- serial out shift register based on reconfigurable MVL- SET is realized with D flip flop, the CLK signal is connected to node Va1 of all the flip flops and the inverted CLK signal is also connected to node Vb1 of all the Flip flops simultaneously. The simulation results are shown in Figures 5.44(a) 5.44(d). The clock signal is given synchronously to all the flip flops. Data at the input is delayed by four clock periods from the input to the output of the shift register. The clock signal is given synchronously to all the flip flops. The Data at "data in", is applied at the FF0 input terminal during the first clock pulse, after the second pulse FF0 data is transferred to FF1 output and new "data in" is transferred to FF0 output. After the third clock, FF2 is replaced by FF1; FF1 is replaced by FF0; and FF0 is replaced by "data in". After the fourth clock, the data originally present at "data in" is at FF3, "output". The "first in" data is "first out" as it is shifted from "data in" to "data out". The each stages of this register can store any one of eight different logic states mentioned in Table 5.5.

48 255 Va1 Vb1 (a) Input signal Va1 (b) input signal Vb1 (c) Serial Input (d) Serial output Figure 5.44 Simulation results of Reconfigurable MVL-SET based SISO register SERIAL - IN PARELLEL OUT The response of reconfigurable MVL-SET based serial in parallel out shift register is shown in Figure 5.45(a) 5.45(g). The four data bits are shifted in by four clock pulses and they are available at Q0 through Q3.After the first clock instant, the data at "data in" appears at Q0, when the second clock occurs, the old Q0 data appears at Q1; Q0 receives next data from "data in". For the third clock, Q1 data is shifted to Q2. After the fourth clock instant, Q2 data is shifted to next flip flop and appears at Q3.

49 256 (a) Input signal Va1 (b) input signal Vb1 (c) Input Data (d) Output Q0 (e) Output Q1 (f) Output Q2 (g) Output Q3 Figure 5.45 Simulation results of reconfigurable MVL-SET based SIPO register PARALLEL IN PARALLEL OUT The response of reconfigurable MVL-SET based serial in parallel out shift register is shown in Figure 5.46(a) 5.46(e). The data present at D 3 through D 0 are loaded in parallel into the registers. These data are shifted in parallel with the instant of clocking and appears at Q 3 through Q 0.

50 257 (a) Input signal Va1 (b) input signal Vb1 (c) Input signal Vc1 (d) Input( D0,D1,D2,D3) (e) Output(Q0,Q1,Q2,Q3) Figure 5.46 Simulation results of reconfigurable SET based PIPO register Reconfigurable MVL-SET Based Flip flop Approach2 In this section, the reconfigurable MVL-SET based memory elements are discussed, in contrast to the memory devices discussed in the previous section, this approach employs two reconfigurable MVL SET inverters as shown in Figure 5.47, to construct a D Flip flop. The clock signal CLK is applied to node Va1, and the inverted clock signal CLK is applied to node V b1 and the reset signal is applied simultaneously to node va1, vb1, Vc1, Vc2 before a new input is applied at the input terminal of D flip flop in

51 258 order to reset the previous values available in each inverters. For CLK = 0, the first inverter changes its state depending on the value of Vin, but the second one does not. For CLK= 1, the first inverter s state is independent of the input signal, while the second one sets and maintains its output based on the signal received from the first one. After this process the output value is maintained in inverter2 and because of the nature of charging and discharging of the SET, the net charge in the output node is maintained constant. Figure 5.47 Reconfigurable (appraoch2) MVL SET based D flip flop If the charge of new data is less than that of output node charge, then the output node maintains its previous state even when clock=1. This problem is overcome by applying the reset signal at inverter1 and inverter2 simultaneously. If the charge at the node is maximum, then the reset voltage is maximum (maximum charge) and the the node Vb1 and Va1 are grounded. This results in output node reset to 0. After the reset process the D flip flop is ready to memorize the new input. As seen in Figure 5.48 (a) (f), the input signal is stored when the clock voltage is high, and after the clock signal is turned off the stored value is maintained up to reset signals applied to both the inverters.

52 259 (a) Input signal Va1 (b) input signal Vb1 (c) Input signal Vin (d) input signal Vc1 (e) Input signal Vc2 (f) output response Figure 5.48 Simulation results of reconfigurable MVL-SET (appraoch2) based D flip flop Reconfigurable MVL- SET Approach2 Based Registers and Counters The terinary state parallel in parallel shift registers and counters are constructed by connecting eight valued D flip flops(approach 2) discussed in the previous section. The each stages of this register and counter can store any one of eight different logic states mentioned in Table 5.5. The operation of the shift register and counters are described in the section 5.3.

53 260 The responses of the parallel in parallel shift register are shown in Figure 5.49(a) (f). Va1 Vb1 (a) Input signal Va1 (b) input signal Vb1 (c) Input signal Vc1 (d) input signal Vc2 (e) Input ( D0,D1,D2,D3) (f) tutputs(q0,q1,q2,q3) Figure 5.49 Simulation results of reconfigurable MVL(appraoch2) based PIPO shift register The reset and control signals for the reconfigurable MVL- SET(approach2) ring counter are shown in Figure 5.50(a) (d). Its simulation results are shown in Figure 5.50(e) ( h).

54 261 (a) Input signal Va1 (b) input signal Vb1 (c) Input data (d) Vc1 of DFF0 and DFF1 (e) Vc2 of DFF 0 (f) Vc2 of DFF1 (g) Output Q1 (h) Output Q0 Figure 5.50 Simulation Results of reconfigurable MVL(appraoch2) based Ring counter Table 5.7 Performance measures of reconfigurable MVL- based memory devices Area Delay(s) Switching energy (W) PDP(J) Inverter x x x10-24 D flip flop x x x10-24 Sift register/counter x x x10-23

55 SEST BASED MEMORY ELEMENTS AND DEVICES In this section, the spin based memory elements have been designed and discussed. The output often depends upon the variable tunnel magnetoresistance. Depends upon the magnetic orientation either in parallel or in anti-parallel direction circuit exhibits different functions, this logic has been exploited for realizing the memory SEST Based Flip Flops D FLIP FLOP The SEST based D flip-flop circuit construction shown in Figure The D-flip flop can be constructed with the help of only two spin based inverters. Each inverter has two SESTs, by varying the tunneling resistances of the SEST; it can be made to work as a D flip flop. The temperature is set to work under 52mK. Further the output characteristics of a SEST depend on the relative magnetization configuration of the ferromagnetic island with respect to the magnetization of the source and the drain, i.e., high current drive capability in parallel magnetization and low current drive capability in antiparallel magnetization. Figure 5.51 SEST based D flip flop

56 263 The magnetization directions of the electrodes are fixed and maintained parallel to each other, whereas the magnetization of the island is reversible. Using the tunneling magneto resistance (TMR) effect between the electrodes and the island, the output current of the SEST is controlled by changing the magnetization direction of the island. The p-type and n-type devices of the inverters are set to parallel and antiparallel respectively. The active high state indicates 7mv and low indicates 0mv. The tunneling resistance of antiparallel configuration is set to as 5 mega ohm and the parallel configurations are set to 0.5 mega ohm. The clock signals CLK and inverted clock signal are applied to node Va1 and Vb1 respectively. For CLK = 0, the first inverter changes its state depending on the value of Vin, but the second one does not. For CLK= 1, the first inverter s state is independent of the input signal, while the second one sets and maintains its output based on the signal received from the first one. Thus the output Q maintains the input value at the corresponding clock pulse. As seen in Figure 5.52 (a) 5.52 (d), the input signal is stored when the clock voltage is high, and the stored value is maintained after the clock signal is turned off. The x axis and y axis are Time (s) and Voltage (v) respectively. Here at the first clk pulse the input value is high (7mv) but at the second clk pulse the input value is logic low (0), thus the output maintains logic high state up to the second clk pulse, after that the Q maintains logic low (0).

57 264 (b) Clock signal (b) Clock bar signal (c) Input D (d) Output Q Figure 5.52 Simulation results of SEST based D flip flop CLOCKED RS FLIP FLOP A RS flip flop is the simplest possible memory element. The inputs R and S are referred to as the Reset and Set inputs, respectively. At the rising edge of each clock the output Q depends on R,S inputs. An R-S flip-flop circuit can thus be obtained by using the circuit construction shown in Figure 5.53 Figure 5.53 SEST based R-S flip flop

58 265 The p-type devices of the both inverters and n-tpye device of the second inverter are set to parallel configurations. The n type device of the first inverter is set to antiparallel configuration. As seen in the circuit diagram the set input is applied at the gating terminals of the first inverter and reset input is applied at the back gate of n-type of inverter 2. This back gate terminal is weighed and threshold into two parts as Cb1 and Cb2. The cb2 is greater than the weightage of the Cb1, the Cb1 is connected to Clk (bias) of inverter2 and Cb2 is connected to R input of R- S flip flop. The clock signal CLK is applied to node Va1, and its inverted clock signal CLK is applied to node Vb1. For CLK = 1, the first inverter changes its state depending on the value of S input, but the second one remains off. For CLK= 0, the first inverter s state is independent of the input signal, while the second one sets and maintains its output based on the signal received from the first one. Thus the output Q maintains the input value still the next clock occurs. When the reset input is made high at the time of next clk pulse the back gate voltage at the n-type device of inverter2 is increased to double the normal operating voltage. It helps the second inverter to establish contact with ground and thus the charge in the load is discharged, now the output Q maintains 0 (logic low). As seen in Figure 5.54 (a) 5.54 (e), at the instant of the first clock pulse the S input value is high (7mv) and R input value is low (0mv),this results in high. But during the second clock pulse the S input value is logic low (0) and R input value is logic high results in output Q maintains logic low state. For both set and reset are logic zero the previous value is maintained in Q. T FLIP FLOP The SEST based T flip flop is shown in Figure It consists of three inverters. The n-tpye devices are set to antiparallel and p-type devices are set to parallel configurations. The clock signal CLK is applied to node Va1, and the inverted clock signal CLK is applied to node Vb1.