! Is it feasible? ! How do we decompose the problem? ! Vdd. ! Topology. " Gate choice, logical optimization. " Fanin, fanout, Serial vs.

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1 ESE 570: Digital Integrated Circuits and VLSI Fundamentals Design Space Exploration Lec 18: March 28, 2017 Design Space Exploration, Synchronous MOS Logic, Timing Hazards 3 Design Problem Problem Solvable! Function: Identify equivalence of two 32bit inputs! Optimize: Minimize total energy! Assumptions: Match case uncommon! Is it feasible? " First, make sure we have a solution so we know our main goal is optimization " Ie Most of the time, the inputs won t be matched! How do we decompose the problem?! Deliberately focus on Energy to complement project " but will still talk about delay! What look like built out of nand2 gates and inverters? 4 5 Knobs Design Space Dimensions! What are the options and knobs we can turn?! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! The choices you make impact area, speed (delay), power 6 7 1

2 Total Power How Reduce Short-Circuit Power?! Static CMOS:! P sc = ac sc V 2 f " P tot a(½c load +C sc )V 2 f+vi s (W/L)e-Vt/(nkT/q)! What can we do to reduce power? # # E = V dd I peak t sc % 1& & % (( $ $ 2' ' 8 9 Gate Logic Family! What gates might we build?! High fanin?! Serial-Parallel?! Considerations for each logic family? " CMOS " Ratioed with PMOS load " Ratioed with NMOS load Sizing Reduce Vdd! How do we want to size gates?! What happens as reduce V? " Energy? " Dynamic " Static " Switching Delay?! How low can we push Vdd?

3 Reduce V dd Increase V th? # τ gd =/I=(CV)/I # I d =(µc OX /2)(W/L)(V gs -V TH ) 2 # τ gd impact? # τ gd α 1/V! What is impact of increasing threshold on " Dynamic Energy? " Leakage Energy? " Delay? Design Space Dimensions Ideas! Vdd! Topology " Gate choice, logical optimization " Fanin, fanout, Serial vs parallel! Gate style / logic family " CMOS, Ratioed (N load, P load)! Transistor Sizing! Vth! We know many things we can do to our circuits! Design space is large! Systematically identify dimensions! Identify continuum (trends) tuning when possible! Watch tradeoffs " don t over-tune! The choices you make impact area, speed (delay), power Classes of Logic Circuits Sequential MOS Logic two stable op pts level triggered Flip-Flop edge triggered one stable op pt One-shot single pulse output no stable op pt Ring Oscillator Combinational Circuits: a Current Output(s) depend ONLY on Current Inputs b Suited to problems that can be solved using truth tables Sequential Circuits or State Machines: a Current Output(s) depend on Current Inputs and Past Inputs via State(s) b Suited to problems that are solved by completing several steps using current inputs and past outputs in a specific order or a sequential manner 19 3

4 Functions Using Sequential Operations Sequential Circuit (or State Machine) Construct Inputs Outputs V o1 Vo2 V o3 20 Present State REGISTER -> Register is used to Store Past Values of State(s) and Output(s) -> Synchronous Sequential Circuit clock, outputs change with clock event -> Asynchronous Sequential Circuit no clock, outputs change after inputs change 21 Next State Clock Synchronous Discipline! Add state elements (registers, latches)! Compute " From state elements " Through combinational logic " To new values for state elements Static Bistable Sequential Circuits Basic Crosscoupled Inverter Static Bistable Sequential Circuits Static Bistable Sequential Circuits Basic Crosscoupled Inverter Basic Crosscoupled Inverter

5 Static Bistable Sequential Circuits Basic Crosscoupled Inverter V OH = V DD Basic Sequential Circuits (Cells)! es! Registers V OL = 0 maintain stable state STATIC: V DD and GND are required to maintain a stable state Basic Bistable Cross-coupled Inverter Pair has no means to apply input(s) to change the circuit's State Register! Level-sensitive device! Positive " Output follows input if CLK high! Negative " Output follows input if CLK low = CLK + CLK In! Edge-triggered storage element! Positive edge-triggered " Input sampled on rising CLK edge! Negative edgetriggered " Input sampled on falling CLK edge Timing Issues Timing Hazards

6 Timing Issues Timing Issues! t su =time data (D) must be valid before CLK edge! t plogic =worst case propagation delay of logic! t c-p =worst case propagation delay of latch! t hold =time data (D) must stay valid after CLK edge! t cdregister =minimum propagation delay of latch! t cdlogic =minimum propagation delay of logic Register from Register from! Build master-slave register from of latches! Control with non-overlapping clocks! Build master-slave register from of latches! Control with non-overlapping clocks Pos Neg Register from Register from! Build master-slave register from of latches! Control with non-overlapping clocks! Build master-slave register from of latches! Control with non-overlapping clocks Negative edge-triggered Register Positive edge-triggered Register Pos Neg Neg Pos

7 CMOS SR NOR2 CMOS SR NOR2 basic crosscoupled inverter * * CMOS SR NOR2 CMOS SR NOR2 SET OP: S = 1, R = 0 basic crosscoupled inverter basic crosscoupled inverter CMOS SR NOR2 RESET OP: R = 1, S = 0 CMOS SR NOR2 HOLD OP: S = 0, R = 0 basic crosscoupled inverter basic crosscoupled inverter

8 CMOS SR NOR2 CMOS SR NOR2 HOLD OP: S = 0, R = 0 basic crosscoupled inverter ACTIVE HIGH * * CMOS SR NAND2 CMOS SR NAND2 basic cross-coupled inverter ACTIVE LOW * * * * Synchronous es Synchronous es NAND SR SR LATCH NOTE: S and R are asynchronous NAND SR SR LATCH NOTE: S and R are asynchronous S/R S /R' S/R S /R' CK CK 48 SET STATE: CK = 1, S = 1, R = 0 => S' = 0, R' = 1 => n+1 = 1, n+1 = 0 RESET STATE: CK = 1, S = 0, R = 1 => S' = 1, R' = 0 => n+1 = 0, n+1 = 1 NOT ALLOWED: CK = 1, S = 1, R = 1 => S' = 0, R' = 0 IS CK = 1, S = 0, R = 0 a HOLD STATE? 49 8

9 Synchronous es! Level-sensitive device! Positive HOLD STATE: CK = 1, S = 0, R = 0 T glitch " Output follows input if CLK high! Negative error due to glitch on S " Output follows input if CLK low = CLK + CLK In R Static CMOS D- Static CMOS D- S If CK = 1 S If CK = 1 LATCH LATCH R If CK = 0, HOLD R If CK = 0, HOLD 18 Transistors CK D S' R' n+1 n SR-Set SR-Reset 0 x 0 0 n n SR-Hold + NO TOGGLE + NO NOT-ALLOWED INPUTS Static CMOS TG D-LATCH 8 Transistors Static CMOS TG D-LATCH CK D CK CK CK 8 Transistors **Transistor level implementation using transmission gates requires fewer transistors

10 Static CMOS TG D-LATCH D-LATCH Timing Requirements When CK = 1 output = D, and tracks D until CK = 0, the D- is referred to positive level triggered When CK 1 to 0, the = D is captured, held (or stored) in the CMOS D Edge Triggered Flip-Flop Impact of Non-ideal Clock on D- Operation Negative D- CLK ideal CLK non-ideal CLK t CLK + τ D t NMOS PMOS Positive D- NMOS PMOS Positive Edge Triggered D Flip-Flop = Negative D- + Positive D- Negative Edge Triggered D Flip-Flop = Positive D- + Negative D- 58 CLK & CLK CLK & CLK + τ D 59 Two-Phase Clocked D- (non-overlapping) Ended here ϕ 1 ϕ 1 ϕ 2 ϕ 2 t t ϕ 1 NMOS PMOS ϕ 1 ϕ 2 ϕ 2 60 Penn ESE 370 Fall Khanna 61 10

11 Logic Comparison Overview Dynamic Logic DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances Outputs are generated in response to input voltage levels and a clock Requires periodic updating or refresh Logic Comparison Overview Comparison of Logic Implementations bit bit_b word P1 P2 N2 N4 A A_b N1 N3 Y WL CBL BL M1 C S DYNAMIC LOGIC GATES: valid logic level are not steady-state op points and depend on temporary storage of charge on parasitic node capacitances Outputs are generated in response to input voltage levels and a clock Requires periodic updating or refresh Ratioed Comparison of Logic Implementations Comparison of Logic Implementations Y Y Ratioed Ratioed

12 Comparison of Logic Implementations Dynamic CMOS Precharge Y V DD Ratioed CK A M p M e Z V DD 1 more robust Dynamic CMOS Precharge Dynamic (Clocked) Logic: Example Z Z of C is complete CK = 0 => Z =? CK = 1 => Z =? Comparison of Static and Dynamic Logic Comparison of Static and Dynamic Logic ADVANTAGES? DISADVANTAGES?

13 Comparison of Static and Dynamic Logic Cascaded Dynamic Logic Cascaded Dynamic Logic Domino Logic Requirements Cascaded Domino CMOS Logic Gates! Single transition " Once transitioned, it is done $ like domino falling! All inputs at 0 during precharge " Outputs pre-charged to 1 then inverted to 0 " Ie Inputs are pre-charge to 0! Non-inverting gates

14 Cascaded Domino CMOS Logic Gates Ideas propagating! Synchronize circuits " to external events (eg Clk) " disciplined reuse of circuitry! Leads to clocked circuit discipline " Uses state holding element (eg es and registers) " Prevents " Timing assumptions " (More) complex reasoning about all possible timings! Dynamic/clocked logic " Only build/drive one pulldown network " Fast transition propagation " Domino Logic allows for cascading Admin! HW 6 due midnight! HW 7 out now " Due midnight " EC due midnight! Start getting groups together for project " Groups of 2 due by 4/6 " Use piazza to find partners 82 14