Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/30/2008

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1 Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 6/3/28 6/3/28 Computer Engineering Basic Element for Sequential CircuitsSR Latch Latch Store one-bit information (two states of and ) Two inputs, R and R and Two outputs and (state) Basic functions of SR-latch S Set SR-latch SR Reset SR-latch SR Hold the current value of SR-latch memory S=R=, take unstable values Prohibited inputs Circuit of SR-latch Timing chart to describe time-variant behavior of SR-latch 6/3/28 Computer Engineering 2

2 Asynchronous or Synchronous Asynchronous Circuits Takes an action when inputs changed States of sequential circuits changed soon after inputs provided No implicit control for circuits unexpected behaviors responding to transit input signals Synchronous Circuits Inputs are accepted when control clock asserted (rising or failing edge of clock) Easy to control circuits Clock should appropriately be adjusted to guarantee the correct behavior of circuits Timing design is very important for synchronous circuits clock Timing of PL Timing of NL Positive logic Negative logic (PL) (NL) Clocking of synchronous circuits Waveform of clock with period T and its activation timing 6/3/28 Computer Engineering 3 Hazard: Malfunction of Asynchronous Circuit Due to Signal Racing ExampleWhat happen on a circuit of Fig.(a) when inputs (X,Y) changed from (,) to (,)? Ideal (expected) Output (,) unchanged because inputs of the latch (S,R) changed from (,) to (,) (See Fig. (b)) But may go into the unstable state If the change of Y is a little bit delayed compared with that of X due to some signal transmission delay from preceding circuits, and the delay of XOR is a bit larger than that of AND(S,R) temporally become (,)(See Fig.) Hazard X Y (b)ideally XOR AND (a) S R Prohibited inputs provided due to signal transmission delay Unstable Unstable (c)but actually 6/3/28 Computer Engineering 4 2

Flip Flop: Building Element for Synchronous Circuits Flip Flop XOR Memory element controlled at the low-high clock transition or high-low clock transition.

3 Flip Flop: Building Element for Synchronous Circuits Flip Flop XOR Memory element controlled at the low-high clock transition or high-low clock transition. (Clock) Synchronized circuit X Y R AND Valid FF activated at Ti Y S R Invalid Edge-triggered FF FF activatedat Ti+ Valid X 6/3/28 S CLK Data held CLK Computer Engineering 5 Sampling points at Ti and Ti+ Inputs, States and Outputs of SR-Flip Flop FF holds one of two states State１ Memorize =) State２ Memorize １ =) Inputs S,R, and (current state) is the current state before sampling at clock edge, Output is the next state after sampling at clock edge. (a) Block diagram Sampling: check inputs and states to take an action 6/3/28 Computer Engineering Clock t Clock t+ State Transition 6 3

4 Behavior of SR-Flip Flop(SR-FF) Edge-triggered SR-FF samples the inputs on the low-to-high (or highto-low) clock transition, and when SR Output becomes Set FF to. SR Output becomes Reset FF to. SR Hold the current state (memory) SR Unstable output Inhibited inputs inhibited (b) State transition table(truth Table) (c ) State Transition diagram 6/3/28 Computer Engineering 7 Behavior of SR-FF (Cont d) Characteristic Equation of SR-FF to describe the next state in terms of the inputs and current state. SR= Prohibited inputs (not allowed) = SR+R =(S+)R = (S+)+R By using SR= =SR+SR+R=S(R+R)+R =S+R Hold Reset Set Hold Reset Set Karnaugh Map 6/3/28 Computer Engineering 8 4

5 JK-FF JK-FF is designed to avoid the prohibited inputs for SR-FF (now called J and K, instead of S and R), and add some circuit to complement the current state (negation of the current state) if two inputs are. Functions of JK-FF JK= = JK= = JK= = JK= = (a) Block diagram (b) State Transition Table (Truth Table) 6/3/28 Computer Engineering 9 JK-FFCont d) Behavior of JK-FF JK= = JK= = JK= = JK= = Characteristic Equation of JK-FF JK (a) Karnaugh Diagram J CK K (b) State Transition Diagram 6/3/28 Computer Engineering 5

Implementation of Edge-Triggered JK-FF 6/3/28 Computer Engineering D-FF: another FF D FF(Data Flip-Flop, or Delay Flip-Flop) Store an input as the internal state.

6 Implementation of Edge-Triggered JK-FF 6/3/28 Computer Engineering D-FF: another FF D FF(Data Flip-Flop, or Delay Flip-Flop) Store an input as the internal state. Output the input at the next clock edge Characteristic Equation D Block diagram 6/3/28 Truth Table Karnaungh Map Computer Engineering State Transition Diagram 2 6

7 One More: T-FF(Toggle Flip-Flop) The toggle FF has a single input that causes the stored state to be complemented when the input is asserted Input T Output Input T(asserted) Output Characteristic equation T+T Block Diagram Truth Table State Transition Diagram 6/3/28 Computer Engineering 3 Relationship among SR-FF, JK-FF, T-FF, and D-FF Characteristic equations of RS, JK, T and D FFs. RS-FF =S+R, SR= JK-FF =J+K T-FF =T+T D-FF =D Excitation Table to describe required inputs of RS, JK, T and D FFs to make a transition from to. RS,JK,T,D?? X means an arbitrary value 6/3/28 Computer Engineering 4 7

Conversion of One Flop-Flop Type to Another: D-FF Implementation by Using JK-FF Excitation Table Karnaugh Map of a circuit to generate J and K inputs Design a combinational circuit to generate

8 Conversion of One Flop-Flop Type to Another: D-FF Implementation by Using JK-FF Excitation Table Karnaugh Map of a circuit to generate J and K inputs Design a combinational circuit to generate appropriate J and K inputs by and D D-FF DFF by using JK FF 6/3/28 Computer Engineering 5 T-FF Implementation by Using JK-FF Exciting Table T X X T X X J=T K=T Design a combinational circuit to generate appropriate J and K inputs by and T CLK Circuit 6/3/28 Computer Engineering 6 8

9 JK-FF Implementation by Using D-FF Excitation Table Design a combinational circuit to generate an appropriate D input by, J and K Circuit?? 6/3/28 Computer Engineering 7 Procedure for Sequential Circuit Design I. Define sets of inputs, outputs, and internal states based on the specification of a desired sequential circuit to be implemented II. Allocate binary numbers to each of inputs, outputs, and states III. Design state transition diagram and/or state transition table (truth table) to clarify the behavior of the circuit based on its specification IV. Decide FF type to be used for the circuit (JK, D, or T) V. Design a combinational circuit to generate appropriate inputs of FFs by using the state transition table and the truth table VI. Implement a sequential circuit by combining the FFs and the designed combinational circuit. Combinational Logic circuit FF FF General configuration of Sequential Logic Circuit 6/3/28 Computer Engineering 8 9

10 Example of Sequential CircuitsCounter Count the number of s provided to the input Octal counter (3-bit),,,,,,,,,... 8 internal states inputz 3-bit for 8 internal states need 3 FFs A, B, C: current states of 3 FFs A, B,C : next state of 3 FFs Z: carry signal generated when counting-up from 8 to State transition table (Truth table) State transition diagram 6/3/28 Computer Engineering 9 Behavior of Octal Counter Waveform (timing chart) of octal counter Describe the behavior in terms of inputs, current state and the next state (outputs) across time Input (Clock signal 6/3/28 Computer Engineering 2

11 Design a Circuit of Octal Counter Using D-FFs Use D-FFs to store internal states of the counter Need a combinational circuit to generate an appropriate inputs for D- FFs Combinational Circuit Block Diagram of an Octal (3-bit) Counter 6/3/28 Computer Engineering 2 Design a Circuit of Octal Counter Using D-FFs(Cont d) Characteristic Eq. of D-FF =D Prepare for D inputs Current state Next state Required inputs for Inputs Outputs Karnaugh Map State Transition Table (truth table) of D-FFs of the counter 6/3/28 Computer Engineering 22

12 Design a Circuit of Octal Counter Using D-FFsCont d) 6/3/28 Computer Engineering 23 Final Design of a 3-bit (Octal) Counter Combinational Logic Circuit 6/3/28 Computer Engineering 24 2

13 If You Want to Use JK-FFs instead of D-FFs In JK-FFs, only J(= ) decides the output when =, or only K(= ) decides the output when =, so A B C A B C J A J B J C K A K B K C * * * * * * * * * * * * * * * * * * * * * * * * :Don t care 6/3/28 Computer Engineering 25 If You Want to Use JK-FFs instead of D-FFs In JK-FFs, only J(= ) decides the output when =, or only K(= ) decides the output when =, so A B C A B C J A J B J C K A K B K C * * * * * * * * * * * * * * * * * * * * * * * * :Don t care 6/3/28 Computer Engineering 26 3

14 If You Want to Use JK-FFs instead of D-FFs Design a combinational circuit to generate the outputs for JK-inputs A B C A B C * * * * = B C = B C J A K A * * * * J A K A A A Z * * * * J B B = C = C J B K B * * * * * * * * J C = K C = * * * * CLK K B J C K C B C C 6/3/28 Computer Engineering 27 Pattern Detector Ex. Detect a specific bit-pattern from - sequence (given -bit by bit) Generate signal when pattern detected. Step : Design a state transition diagram for a -pattern detector Input X Output signal of detected or not. There are four states: *(initial): State : State : State : 2 FFs needed. 6/3/28 Computer Engineering 28 4

15 Design of a -pattern Detector using D-FFs Step 2: Design a state transition table (truth table) and derive a logical equation for inputs of FFs of a -pattern detector When using two D-FFs, and input X ( or ) defined, design a combination circuit. Karnaugh Map State transition table (truth table) Logical Equations for inputs of D-FFs 6/3/28 Computer Engineering 29 A Circuit of a Bit-Pattern- Detector 6/3/28 Computer Engineering 3 5

Register: On-Chip Memory using D-FFs Register On-chip temporal storage for data processing Fast data access achieved compared to data access to/from off-chip memory Arithmetic Units use data on

16 Register: On-Chip Memory using D-FFs Register On-chip temporal storage for data processing Fast data access achieved compared to data access to/from off-chip memory Arithmetic Units use data on Registers instead of directory using data on off-chip memory Functions of Register: When LD=, data loaded into registers When LD=, hold the data 4-bit register implementation Block diagram of 4-bit register using D-FFs When CLR=, D- FF are reset to 6/3/28 Computer Engineering 3 Computer System Architecture: General Model Processor Memory 6/3/28 Computer Engineering 32 6

17 Sift Register Register with a functionality of data shifting Block diagram Implementation using D-FFs 4-bit shift register 6/3/28 Computer Engineering 33 Important!: Class Schedule in July, August and September 7/7 Regular Class 7/4 Regular Class (Final class) 7/2 No class National holiday 7/28 No scheduled class (I will be out of office) 8/4 Final Examination You may bring the handouts of the class that I have provided Complementary final examination for students who cannot take the test on 8/4 will be scheduled on one day between July 5-July22 Sing up today or 7/7 (firm deadline) You should describe the reason for the absence on 8/4 You may bring the handouts of the class that I have provided 9/8 additional examination for those who cannot pass the 8/4 exam The results of the 8/4 exam will be announce in the week of 8/4, on the bulletin board of the mechanical engineering office. 6/3/28 Computer Engineering 34 7

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7//2 Ver. 72 7//2 Computer Engineering What is a Sequential Circuit? A circuit consists of a combinational logic circuit and internal memory