GATE Online Free Material

Size: px
Start display at page:

Download "GATE Online Free Material"

Transcription

1 Subject : Digital ircuits GATE Online Free Material 1. The output, Y, of the circuit shown below is (a) AB (b) AB (c) AB (d) AB 2. The output, Y, of the circuit shown below is (a) 0 (b) 1 (c) B (d) A 3. The output, Y, of the circuit shown below is (a) ( x y) ( x y z) (b) ( x y) ( x y z) (c) ( x y) ( x y z) (d)( x y) ( x y z) 4. The diagram given below represents (a) Demorgans law (b) Associative Law (c) Product of sum form (d) Sum of product form 5. The output of this circuit is always

2 (a) 1 (b) 0 (c) A (d) A 6. The gray equivalent of ( 25) 10 is (a) (b) (c) (d) A signed integer has been stored in a byte using 2 s complement format. We wish to store the same integer in 16-bit word. We should copy the original byte to the less significant byte of the word and fill the more significant byte with (a) 0 (b) 1 (c) equal to the MSB of the original byte (d) omplement of the MSB of the original byte. 8. The output X is (a) MN (b) N( M ) (c) M ( N) (d) ( M N) 9. The output Z is (a) A B (b) AB (c) AB B A (d) all the above 10. The output Z is (a) A B ( D)( E F) (b) AB D EF (c) A B ( D)( E F) (d) AB D EF

3 11. The output Y is (a) AB AB (b) AB AB (c) AB AB (d) AB AB 12. The minimum number of NOR gates required to implement A( A B)( A B ) is equal to (a) 0 (b) 3 (c) 4 (d) The Boolean expression A B is eqiuivalent to (a) A A B (b) B A B AB (c) A B B AB (d) AB AB AB AB 14. The expression A AB AB ABD ABDE Is equivalent to (a) A AB D E (b) A B DE (c) A B D DE (d) A B D E 15. The simplified form of a logic function Y A( B ( AB A)) is (a) AB (b) AB (c) AB (d) AB 16. The reduced form of the Boolean expression of Y ( AB).( AB) is (a) A B (b) A B (c) AB AB (d) AB AB 17. In fig the input condition, needed to produce X 1, is (a) A 1, B 1, 0 (b) A 1, B 1, 1 (c) A 0, B 1, 1 (d) A 1, B 0, If the output waveform from an OR gate is always HIGH, one of its input is being held permanently HIGH. The statement, which is always true, is (a) Both 1 and 2 (b) Only 1 (c) Only 2 (d) None of the above 19. If the X and Y logic inputs are available and their complements X and Y are not available, the minimum number of two-input NAND required to implement X Y is (a) 4 (b) 5 (c) 6 (d) If the input to the digital circuit shown in fig. consisting of a cascade of 20 XOR gates is X, then the output Y is equal to

4 (a) X (b) X (c) 0 (d) A boolean function of two variables x and y is defined as follows: f ( 0, 0) f ( 0, 1) f ( 1, 1) 1; f ( 1, 0) 0 Assuming complements of x and y are not available, a minimum cost solution for realizing f using 2- input NOR gates and 2-input OR gates (each having unit cost) would have a total cost of (a) 1 units (b) 2 units (c) 3 units (d) 4 units 22. In the network of the figure shown below, the output can be written as (a) X0X1X3X5 X2X4X5... Xn 1 Xn 1 Xn (b) X X X X X X X... X... X X n n 1 n (c) X X X X... X X X X... X... X X n n n 1 n (d) X X X X... X X X X... X... X X X n n n 1 n 2 n 23. A Boolean function Z AB is to be implement using NAND and NOR gate. Each gate has unit cost. Only the variables A, B and are available. If both gates are available then minimum cost is (a) 2 units (b) 3 units (c) 4 units (d) 6 units 24. Simplify the following expression into sum of products using Karnaugh map F(A,B,,D) = (1,3,4,5,6,7,9,12,13) (a) A( B D) (b) A( B D) ( B D) (c) ( B D ) (d) A( B D) ( A D ) 25. F AB AB AB AB AB (a) F ( A B ) (b) F ( A B ) (c) F ( A B ) (d) F ( A B ) 26. XY YZ YZ (a) XY Z (b) XY Z (c) XY Z (d) XY Z 27. AB AB AB (a) A B (b) A B (c) A B (d) A B 28. A AB AB (a) A B (b) A B (c) A B (d) A B 29. AB AB AB AB (a) AB B A (b) AB B A (c) AB B A (d) AB B A 30. The Boolean expression Y ABD ABD ABD ABD can be minimized to (a) Y ABD AB AD (b) Y ABD BD ABD (c) Y ABD AD ABD ABD (d) Y ABD BD ABD

5 31. In the Karnaugh map shown below, X denotes a don t care term. What is the minimal form of the function represented by the Karnaugh map? (a) bd ad (b) ab bd abd (c) bd adb (d) ab bd ad 32. The X = ( A + B )(A + B + ) can be converted to standard form (a) (A +B + )( A + B + )(A + B + ) (b) (A +B + )( A + B + )(A + B + (c) (A +B + )( A + B + )(A + B + ) (d) (A +B + )( A + B + ) 33. Simplify the following expression using three variable maps. 1 F(x,y,z)= (0,1,5,7) 2 F(x,y,z)= (1,2,3,6,7) 3 F(x,y,z)= (3,5,6,7) 4 F(x,y,z)= (0,2,3,4,6) And find out which one of these will produce F xy yz zx (a) 1 (b) 2 (c) 3 (d) The 3-variable Karnaugh Map (K-Map) has cells for min or max terms (a) 8 (b) 12 (c) 16 (d) Sum term (Max term) is implemented using gates (a) OR (b) AND (c) NOT (d) OR-AND 36. The Karnaugh map shown below can be simplified to (a) A B (b) A B (c) A B (d) A B 37. The Karnaugh map shown below can be simplified to (a) B A (b) B A (c) B A (d) B A 38. Simplify the following expression using three variable maps. F( A, B, ) ( 0, 1, 5, 7) (a) A B (b) A B (c) A B (d) A B

6 AB A A B 39. Simplify the following expression using three variable maps. F( A, B, ) ( 1, 2, 3, 6, 7) (a) B A (b) A B (c) A B (d) A B 40. Simplify the following expression using three variable maps. F( A, B, ) ( 0, 1, 6, 7) (a) A AB (b) A B (c) AB AB (d) A B 41. Simplify the following expression using four variables maps. F( A, B,, D) ( 1, 4, 5, 6, 7 ) (a) A B (b) D AB (c) D AB (d) D AB 42. Simplify the following expression using four variables maps, F( A, B, ) ( 0, 1, 5, 8, 9) (a) AD AB (b) A B (c) AD A (d) AD AD 43. Simplify the following expression using four variables maps, F( A, B,, D) ( 0, 2, 4, 5, 6, 7, 8, 10, 12, 13, 15) (a) D BD BD (b) D BD B (c) D AD BA (d) D AD B 44. onsider the founction F( A, B,, D) ( 1, 2, 4, 5, 6, 7, 8, 10, 13, 15) and draw karnaugh map, then the essential prime impliecants are (a) D, BD, BD (b) D, BD, BD (c) D, BD, BD (d) D, BD, BD Linked uestions 45 AND 46 onsider the founction F( A, B,, D) ( 2, 3, 5, 7, 10, 11, 14, 15 ) 45. The essential prime implicants are (a) A, D, BD and ABD (c) A, D, BD and ABD (b) A,D, BD and ABD (d) A, D, BD and ABD 46. The simplified expression for F is (a) A D BD ABD (b) A D BD ABD (c) A D BD ABD (d) A D BD ABD

7 Problem 47 to 48 are linked onsider the founction F( A, B, ) ( 0, 5, 7, 8, 10, 13) 47. The essential prime impliecants are (a) A, AD (b) A, AD (c) A, AD (d) A, AD 48. The non-essential prime implicants are (a) D, BD, AB and ABD (c) D, BD, ABD and AB (b) D, BD, AB and ABD (d) D, BD, ABD and AB 49. The initial contents of 4- bit serial in-parallel out right shift, register shown below is After three clock pulses are applied, the contents of shift register will be (a) 0000 (b)0101 (c)1010 (d) Match correctly ounter Number of states A.Ripple counter 1. 2 N B.Johnson counter 2.N.Ring counter 3.2N D.Sequence counter 4.2 N - 1 (A) (B) () (D) (a) (b) (c) (d) The present output n of an edge triggered JK flip flop is logic O. if J=1 then n 1 (a) annot be determined (b)will be logic O (c)will be logic 1 (d)will race around 52. Which of the following condition must be met to avoid race around problem where, t p is propagation delay of the NAND gate t is pulse width and T is period of pulse train? (a) t tp T (b) t 2t p T (c) T 2 t tp (d) T tp 2 t 53. A master-salve F/F has the characteristic that (a)hange in the input is immediately reflected in the output (b)hange in the output occurs when the state of the master is affected (c)hange in the output occurs when the state of slave is affected (d)both the master and the slave state are affected at the same time

8 54. If a counter having 10 FFs is initially at 0, what count will it hold after 2060 pulses? (a) (b) (c) (d) A pulse train with a frequency of 1 MHz is counted using a modulo 1024 ripple-counter built with J-K flip-flops. For proper operation of the counter the maximum permissible propagation delay per flip-flop stage is (a) 100 n sec (b) 50 n sec (c) 20 n sec (d) 10 n sec 56. In a 4 bit counter, the outputs of 3 JK FFs from MSB downward are connected to NAND gate whose output is connected to LR. (a) It is a MOD-14 counter (b) It is a MOD-13 counter (c) It is a divide by-13 counter (d) It is a divide by-14 counter 57. The output of a JK flipflop with asynchronous preset and clear inputs is 1. The output can be changed to 0 with one of the following conditions. (a) By applying J = 0, K = 0 and using a clock. (b) By applying J = 1, K = 0 and using the clock. (c) By applying J = 1, K = 1 and using the clock. (d) By applying a synchronous preset input. 58. A shift register can be used for (a)parallel to serial conversion (b) serial to parallel conversion (c)digital delay line (d) all of these 60. The circuit shown in the figure below is a Input D D D Output Lock (a) full adder (b) half adder (c) shift register (d) 2-bit multiplexer 61. What logic function is performed by the circuit shown below? Input D D D Output Lock (a) ring counter (b) ripple counter (c) full adder (d) half adder 61. onsider the counter shown below: What is the modulo (number of pressing states) of this counter? (a) 3 (b) 6 (c) 8 (d) Modulo cannot be determined from the circuit 62. The inputs of the J-K flip-flop, shown below are

9 J LK K If a single clock pulse is applied, then device will (a) toggle (b) set (c) rest (d) not change states 63. A ring counter same as (a) up-down counter (b) parallel-counter (c) shift register (d) none of these 64. The circuit shown in the figure given below LEAR Output (a) is an oscillating circuit and its output is a square wave (b) is one whose output remains stable in 1 state (c) is one having output semains stable 0 state (d) having a single pulse of 3 times propagation delay 65. A mod-2 counter followed by a mod-5 counter is (a) same as a mod-5 counter followed by a mod-2 counter (c) a mod-7 counter 66. A mod-2 counter followed by a mod-5 counter is (a) same as a mod-5 counter followed by a mod-2 counter (c) a mod-7 counter (b) a decade counter (d) none of these (b) a decade counter (d) none of these 67. A 4- bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required for change of state will be (a) 25 ns (b) 50 ns (c) 75 ns (d) 100 ns 68. ircuit in the given figure produces the output sequence J J J J K K K K O/P LOK (a) (b) (c) (d) onsider the circuit given below with initial state 0 1, The state of the circuit is given by the value

10 D 0 0 D D 2 LSB MSB lock The correct state sequence of the circuit is (a) 1, 3, 4, 6, 7, 5, 2 (b) 1, 2, 5, 3, 7, 6, 4 (c) 1, 2, 7, 3, 5, 6, 4 (d) 1, 6, 5, 7, 2, 3, The following arrangement of master-slave flip flops has the initial state of P, as 0, 1 respectively. After three clock cycles, the output state P, respectively are P 0 I J K D lock (a) 1,0 (b) 1,1 (c) 0,0 (d) 0,1 71. onsider the circuit shown below: +5V R 1 Input pulses J FF1 FF LK K LR FF2 J FF1 J J FF3 LK LK LK LR K LR LR K K The input data is fixed at a LOW level and the output values are as shown in the figure. The number of clock pulses required to give an output of 0000 is (a) 2 (b) 3 (c) 4 (d) The number of clock pulses needed to shift one byte of data from input to the output of a 4-bit shift register is (a) 11 (b) 12 (c) 16 (d) The logic circuit shown below is a 3-bit

11 R B lock input J J J LK LK LK K K K (a) shift register (b) asynchronous binary up counter (c) asynchronous binary down-counter (d) synchronous binary up counter 74. For the initial state of 000, the function performed by the arrangement of the J-K flip-flop in the given figure is J J J K K K (a) shift-register (c) mod-6 counter LOK (b) mod-3 counter (d) mod-2 counter 75. The three-stage Johnson counter as shown in figure is clocked at a constant frequency of f c from the starting state of The frequency of output will be J J 1 J K K 2 2 K LK fc (a) 8 fc (b) 6 fc (c) 3 fc (d) The modulus of the counter shown below is (a) 12 (b) 13 (c) 14 (d) In the above problem the frequency of the FF3 is

12 (a) 1khz (b) 10 khz (c) 100 khz (d) 1 mhz 78. Refer to the counter shown in the figure; determine the count sequence of this counter, (a) 100,001,010,011,100,101,110,000 (b) 110,001,010,011,100,101,110,000 (c) 000,001,010,011,100,101,110,000 (d) 111,001,010,011,100,101,110, A 100 stage serial-in/serial-out shift resistor is clocked at 100 khz. How long will the data will be delayed in passing trough the resistor. 1ms (a) 10ms (b) 100ms (c) 0.1ms (d) 1ms 80. The Boolean expression for the output f of the multiplexer shown below is (a) P R (b) P R (c) P R (d) P R 81. The output f of the 4-to-1 MUX shown in the given figure is (a) xy x (b) x y (c) x y (d) xy x 82. The output F of the multiplexer circuit shown in the given figure can be represented by MUX Select B A

13 (a) AB B A B (b) A B (c) (d) AB AB AB 83. onsider the MUX-circuit shown below: (a) 4: 1 Multiplexer (b) 2:1 multiplexer (c) 4:2 multiplexer (d) 3:1 Multiplexer 84. For the logic circuit shown below the input Y is (a) A B (b) A B (c) A B (d) A B 85. onsider 3:8 decoder as shown below, the output ff 1 2 is (a) x0x1 x 2 (b) x0 x1 x2 (c) 1 (d) 0 Solution: Given, f1 m 0,4,6,2 f2 m 1,3,5,7 ff 1 2 0

14 86. The output of the logic circuit is (a) Y A B (b) Y A B (c) Y A B (d) Y 87. The output of the logic circuit is AB (a) Y AB D (b) Y ABD (c) Y AB D (d) Y ABD 88. The output of the logic circuit is (a) Y ABD (b) Y AB D (c) Y AB D (d) Y A B D

15 89. The output of the logic circuit is (a) Y ABD (b) 90. The output of the logic circuit is Y A B D (c) Y AB D (d) Y AB D (a) Y A B (b) Y A B (c) Y A B (d) Y AB 91. Find the conversion time and conversion rate of a Successive Approximation A/D converter which uses a 2 MHz clock and a 5-bit binary ladder containing 8V reference. (a) 2.5 s, 400,000 (b) 5 s, 400,000 (c) 5 s, 200,000 (d) 2.5 s, 200, bit R-2R ladder D/A converter has a reference voltage of 6.5V. It meets standard linearity. Find (i) The Resolution in Percent. (ii) The output voltage for the word (a) 2.59%,2.84V (b) 1.59%,2.84V (c) 1.59%,1.42V (d) 1.59%,3.84V

16 93. Refer to Figure. This BD D/A converter has a step size of 6.25 mv. Determine the full-scale output. (a) V (b) V (c) V (d) V 94. A 5-bit DA produces an output voltage of 0.2V for a digital input of Find the value of the output voltage for an input of What is the resolution of this DA? (a) V (b) V (c) V (d) V 95. A certain binary-weighted-input DA has a binary input of If a HIGH = +3.0 V and a LOW = 0 V, what is V out? (a) 4.25V (b) 3.15V (c)-3.25 V (d) -3.15V 96. How many bits are required at the input of a ladder D/A converter, if it is required to give a resolution of 5mV and if the full scale output is +5V. Find the %age resolution. (a) 20, 0.1% (b) 10, 0.2 % (c) 10, 0.2 % (d) 10, 0.1% uestions 97 and 98 are linked A counter type A/D converter is shown in the figure.

17 97. Determine the conversion time of a 12-bit A/D for an input clock frequency of 1 MHz. (a) ms (b) ms (c) ms (d) ms 98. Determine the averae conversion time of a 12-bit A/D for an input clock frequency of 1 MHz. (a) ms. (b) ms. (c)3.047 ms. (d) ms. 99. A PLA realization is shown below f X, X, X? X X (a) X X (b) X2X0 X1X2 (c) X2 X0 (d) X2 X f2 X2, X1, X0? (a) m 1,2,5,6 (b) m 1,2,6,7 (c) m 2,3,4 (d) None of these 101. A Program that translates english-like words of a high level language into the machine language of a computer is (a) A compiler (b) Assembler (c) Interpreter (d) Source code 102. In a flag register of Where does the sign flag and parity flag set? (a) D7 and D 8 (b) D6 and D 4 (c) D7 and D 2 (d) D7 and D If Register B contains 28H, and Accumulator 97H. What will be the content of Register after the following program has been executed? MOV A, B MOV, A MOV B, MOV, B

18 (a) 28 H (b) AA H (c) 97 H (d) OOH 104. The following program stats at location 0100 H LXI SP, 00FF LXI H,0701 H MVI A, 20H SUB M The content of the accumulator when the program counter reach 0109 H is (a) 20 H (b) 02 H (c) 00 H (d) FF H 105. The following program is run on an 8085 microprocessor, Memory address in Hex Instruction 2000 LXI SP, PUSH H 2004 PUSH D 2005 ALL POP H 2009 HLT As the completion of execution of the program, the program counter of the 8085 contains and the stack pointer contains. (a) 2050,OFF (b) 2251, OFF (c) 1025 OF (d) 1125,OF 106. An Intel 8085 processor is executing the program given below. MVIA,10H MVIB,10H BAK:NOP ADD B RL JN BAK HLT The number of times that the opertaion NOP will be executed is equal to - (a) 1 (b) 2 (c) 3 (d) The following program is written for an 8085 microprocessor to add bytes located at memory address 1 FFE and 1FFF MOV B,M INR L MOV A,M ADD B INR L MOV M,A XOR A On completion of the execution of the program, the result of addition is found - (a) in the register A (b) at the memory address 1000 (c) at the memory address 1F00 (d) at the memory address 2000

IES Digital Mock Test

IES Digital Mock Test . The circuit given below work as IES Digital Mock Test - 4 Logic A B C x y z (a) Binary to Gray code converter (c) Binary to ECESS- converter (b) Gray code to Binary converter (d) ECESS- To Gray code

More information

Fan in: The number of inputs of a logic gate can handle.

Fan in: The number of inputs of a logic gate can handle. Subject Code: 17333 Model Answer Page 1/ 29 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

Laboratory Manual CS (P) Digital Systems Lab

Laboratory Manual CS (P) Digital Systems Lab Laboratory Manual CS 09 408 (P) Digital Systems Lab INDEX CYCLE I A. Familiarization of digital ICs and digital IC trainer kit 1 Verification of truth tables B. Study of combinational circuits 2. Verification

More information

DIGITAL ELECTRONICS QUESTION BANK

DIGITAL ELECTRONICS QUESTION BANK DIGITAL ELECTRONICS QUESTION BANK Section A: 1. Which of the following are analog quantities, and which are digital? (a) Number of atoms in a simple of material (b) Altitude of an aircraft (c) Pressure

More information

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished

Number system: the system used to count discrete units is called number. Decimal system: the number system that contains 10 distinguished Number system: the system used to count discrete units is called number system Decimal system: the number system that contains 10 distinguished symbols that is 0-9 or digits is called decimal system. As

More information

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28

Winter 14 EXAMINATION Subject Code: Model Answer P a g e 1/28 Subject Code: 17333 Model Answer P a g e 1/28 Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER-16 EXAMINATION Model Answer

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) SUMMER-16 EXAMINATION Model Answer Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

CONTENTS Sl. No. Experiment Page No

CONTENTS Sl. No. Experiment Page No CONTENTS Sl. No. Experiment Page No 1a Given a 4-variable logic expression, simplify it using Entered Variable Map and realize the simplified logic expression using 8:1 multiplexer IC. 2a 3a 4a 5a 6a 1b

More information

EECS 150 Homework 4 Solutions Fall 2008

EECS 150 Homework 4 Solutions Fall 2008 Problem 1: You have a 100 MHz clock, and need to generate 3 separate clocks at different frequencies: 20 MHz, 1kHz, and 1Hz. How many flip flops do you need to implement each clock if you use: a) a ring

More information

Digital Logic Circuits

Digital Logic Circuits Digital Logic Circuits Let s look at the essential features of digital logic circuits, which are at the heart of digital computers. Learning Objectives Understand the concepts of analog and digital signals

More information

Department of Electronics and Communication Engineering

Department of Electronics and Communication Engineering Department of Electronics and Communication Engineering Sub Code/Name: BEC3L2- DIGITAL ELECTRONICS LAB Name Reg No Branch Year & Semester : : : : LIST OF EXPERIMENTS Sl No Experiments Page No Study of

More information

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER

MAHARASHTRA STATE BOARD OF TECHNICAL EDUCATION (Autonomous) (ISO/IEC Certified) MODEL ANSWER Important Instructions to examiners: 1) The answers should be examined by key words and not as word-to-word as given in the model answer scheme. 2) The model answer and the answer written by candidate

More information

logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs

logic system Outputs The addition of feedback means that the state of the circuit may change with time; it is sequential. logic system Outputs Sequential Logic The combinational logic circuits we ve looked at so far, whether they be simple gates or more complex circuits have clearly separated inputs and outputs. A change in the input produces

More information

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1

LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM. 2012/ODD/III/ECE/DE/LM Page No. 1 LOGIC DIAGRAM: HALF ADDER TRUTH TABLE: A B CARRY SUM K-Map for SUM: K-Map for CARRY: SUM = A B + AB CARRY = AB 22/ODD/III/ECE/DE/LM Page No. EXPT NO: DATE : DESIGN OF ADDER AND SUBTRACTOR AIM: To design

More information

Module -18 Flip flops

Module -18 Flip flops 1 Module -18 Flip flops 1. Introduction 2. Comparison of latches and flip flops. 3. Clock the trigger signal 4. Flip flops 4.1. Level triggered flip flops SR, D and JK flip flops 4.2. Edge triggered flip

More information

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM

LIST OF EXPERIMENTS. KCTCET/ /Odd/3rd/ETE/CSE/LM LIST OF EXPERIMENTS. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation

More information

ELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100

ELECTRONIC CIRCUITS. Time: Three Hours Maximum Marks: 100 EC 40 MODEL TEST PAPER - 1 ELECTRONIC CIRCUITS Time: Three Hours Maximum Marks: 100 Answer five questions, taking ANY TWO from Group A, any two from Group B and all from Group C. All parts of a question

More information

1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as

1. The decimal number 62 is represented in hexadecimal (base 16) and binary (base 2) respectively as BioE 1310 - Review 5 - Digital 1/16/2017 Instructions: On the Answer Sheet, enter your 2-digit ID number (with a leading 0 if needed) in the boxes of the ID section. Fill in the corresponding numbered

More information

Page 1. Last time we looked at: latches. flip-flop

Page 1. Last time we looked at: latches. flip-flop Last time we looked at: latches flip flops We saw that these devices hold a value depending on their inputs. A data input value is loaded into the register on the rise of the edge. Some circuits have additional

More information

Practical Workbook Logic Design & Switching Theory

Practical Workbook Logic Design & Switching Theory Practical Workbook Logic Design & Switching Theory Name : Year : Batch : Roll No : Department: Second Edition Fall 2017-18 Dept. of Computer & Information Systems Engineering NED University of Engineering

More information

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA

COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC CSCD211- DEPARTMENT OF COMPUTER SCIENCE, UNIVERSITY OF GHANA COMPUTER ORGANIZATION & ARCHITECTURE DIGITAL LOGIC LOGIC Logic is a branch of math that tries to look at problems in terms of being either true or false. It will use a set of statements to derive new true

More information

CS302 - Digital Logic Design Glossary By

CS302 - Digital Logic Design Glossary By CS302 - Digital Logic Design Glossary By ABEL : Advanced Boolean Expression Language; a software compiler language for SPLD programming; a type of hardware description language (HDL) Adder : A digital

More information

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING (Regulation 2013) EE 6311 LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB MANUAL 1 SYLLABUS OBJECTIVES: Working Practice in simulators / CAD Tools / Experiment

More information

Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006

Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006 COE/EE2DI4 Midterm Test #1 Fall 2006 Page 1 Dr. Nicola Nicolici COE/EE2DI4 Midterm Test #1 Oct 18, 2006 Instructions: This examination paper includes 10 pages and 20 multiple-choice questions starting

More information

Electronics. Digital Electronics

Electronics. Digital Electronics Electronics Digital Electronics Introduction Unlike a linear, or analogue circuit which contains signals that are constantly changing from one value to another, such as amplitude or frequency, digital

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2): 48 million IBM PowerPC 75FX (22): 38 million IBM/Apple PowerPC

More information

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI

SRV ENGINEERING COLLEGE SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI SEMBODAI RUKMANI VARATHARAJAN ENGINEERING COLLEGE SEMBODAI 6489 (Approved By AICTE,Newdelhi Affiliated To ANNA UNIVERSITY::Chennai) CS 62 DIGITAL ELECTRONICS LAB (REGULATION-23) LAB MANUAL DEPARTMENT OF

More information

NODIA AND COMPANY. Model Test Paper - I GATE Digital Electronics. Copyright By Publishers

NODIA AND COMPANY. Model Test Paper - I GATE Digital Electronics. Copyright By Publishers No part of this publication may be reproduced or distributed in any form or any means, electronic, mechanical, photocopying, or otherwise without the prior permission of the author. Model Test Paper -

More information

Computer Architecture and Organization:

Computer Architecture and Organization: Computer Architecture and Organization: L03: Register transfer and System Bus By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU Outlines

More information

ELECTRONICS AND COMMUNICATION ENGINEERING

ELECTRONICS AND COMMUNICATION ENGINEERING ELECTRONICS AND COMMUNICATION ENGINEERING Q1. A transmission line of characteristic impedance 50 Ω is terminated by a 50 Ω load. When excited by a sinusoidal voltage source at 10 GHz the phase difference

More information

COLLEGE OF ENGINEERING, NASIK

COLLEGE OF ENGINEERING, NASIK Pune Vidyarthi Griha s COLLEGE OF ENGINEERING, NASIK LAB MANUAL DIGITAL ELECTRONICS LABORATORY Subject Code: 2246 27-8 PUNE VIDYARTHI GRIHA S COLLEGE OF ENGINEERING,NASHIK. INDEX Batch : - Sr.No Title

More information

Sr. No. Instrument Specifications. TTL (Transistor-Transistor Logic) based on bipolar junction transistors

Sr. No. Instrument Specifications. TTL (Transistor-Transistor Logic) based on bipolar junction transistors MIT College of Engineering, Pune. Department of Electronics & Telecommunication (Electronics Lab) EXPERIMENT NO 01 TITLE OF THE EXPERIMENT: Verify four voltage and current parameters for TTL and CMOS (IC

More information

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT

FUNCTION OF COMBINATIONAL LOGIC CIRCUIT HAPTER FUNTION OF OMBINATIONAL LOGI IRUIT OUTLINE HALF-ADDER ANF FULL ADDER IRUIT -BIT PARALLEL BINARY RIPPLE ARRY ADDER -BIT PARALLEL BINARY ARRY LOOK- AHEAD ADDER BD ADDER IRUIT DEODER ENODER MULTIPLEXER

More information

Digital Electronics Course Objectives

Digital Electronics Course Objectives Digital Electronics Course Objectives In this course, we learning is reported using Standards Referenced Reporting (SRR). SRR seeks to provide students with grades that are consistent, are accurate, and

More information

Linear & Digital IC Applications (BRIDGE COURSE)

Linear & Digital IC Applications (BRIDGE COURSE) G. PULLAIAH COLLEGE OF ENGINEERING AND TECHNOLOGY Accredited by NAAC with A Grade of UGC, Approved by AICTE, New Delhi Permanently Affiliated to JNTUA, Ananthapuramu (Recognized by UGC under 2(f) and 12(B)

More information

R.B.V.R.R. WOMEN S COLLEGE (AUTONOMOUS) Narayanaguda, Hyderabad. ELECTRONIC PRINCIPLES AND APPLICATIONS

R.B.V.R.R. WOMEN S COLLEGE (AUTONOMOUS) Narayanaguda, Hyderabad. ELECTRONIC PRINCIPLES AND APPLICATIONS R.B.V.R.R. WOMEN S COLLEGE (AUTONOMOUS) Narayanaguda, Hyderabad. DEPARTMENT OF PHYSICS QUESTION BANK FOR SEMESTER V PHYSICS PAPER VI (A) ELECTRONIC PRINCIPLES AND APPLICATIONS UNIT I: SEMICONDUCTOR DEVICES

More information

Brought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja.

Brought to you by. Priti Srinivas Sajja. PS01CMCA02 Course Content. Tutorial Practice Material. Acknowldgement References. Website pritisajja. Brought to you by Priti Srinivas Sajja PS01CMCA02 Course Content Tutorial Practice Material Acknowldgement References Website pritisajja.info Multiplexer Means many into one, also called data selector

More information

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer

JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS. 6 Credit Hours. Prepared by: Dennis Eimer JEFFERSON COLLEGE COURSE SYLLABUS ETC255 INTRODUCTION TO DIGITAL CIRCUITS 6 Credit Hours Prepared by: Dennis Eimer Revised Date: August, 2007 By Dennis Eimer Division of Technology Dr. John Keck, Dean

More information

DIGITAL LOGIC COMPUTER SCIENCE

DIGITAL LOGIC COMPUTER SCIENCE 29 DIGITL LOGIC COMPUTER SCIENCE Unit of ENGINEERS CREER GROUP Head O ce: S.C.O-2-22 - 23, 2 nd Floor, Sector-34/, Chandigarh-622 Website: www.engineerscareergroup.in Toll Free: 8-27-4242 E-Mail: ecgpublica

More information

Objective Questions. (a) Light (b) Temperature (c) Sound (d) all of these

Objective Questions. (a) Light (b) Temperature (c) Sound (d) all of these Objective Questions Module 1: Introduction 1. Which of the following is an analog quantity? (a) Light (b) Temperature (c) Sound (d) all of these 2. Which of the following is a digital quantity? (a) Electrical

More information

Code No: R Set No. 1

Code No: R Set No. 1 Code No: R05310402 Set No. 1 1. (a) What are the parameters that are necessary to define the electrical characteristics of CMOS circuits? Mention the typical values of a CMOS NAND gate. (b) Design a CMOS

More information

Combinational Logic Circuits. Combinational Logic

Combinational Logic Circuits. Combinational Logic Combinational Logic Circuits The outputs of Combinational Logic Circuits are only determined by the logical function of their current input state, logic 0 or logic 1, at any given instant in time. The

More information

Written exam IE1204/5 Digital Design Friday 13/

Written exam IE1204/5 Digital Design Friday 13/ Written exam IE204/5 Digital Design Friday 3/ 207 08.00-2.00 General Information Examiner: Ingo Sander. Teacher: Kista, William Sandqvist tel 08-7904487 Teacher: Valhallavägen, Ahmed Hemani 08-7904469

More information

R & D Electronics DIGITAL IC TRAINER. Model : DE-150. Feature: Object: Specification:

R & D Electronics DIGITAL IC TRAINER. Model : DE-150. Feature: Object: Specification: DIGITAL IC TRAINER Model : DE-150 Object: To Study the Operation of Digital Logic ICs TTL and CMOS. To Study the All Gates, Flip-Flops, Counters etc. To Study the both the basic and advance digital electronics

More information

I.E.S-(Conv.)-2007 ELECTRONICS AND TELECOMMUNICATION ENGINEERING PAPER - II Time Allowed: 3 hours Maximum Marks : 200 Candidates should attempt Question No. 1 which is compulsory and FOUR more questions

More information

DELD MODEL ANSWER DEC 2018

DELD MODEL ANSWER DEC 2018 2018 DELD MODEL ANSWER DEC 2018 Q 1. a ) How will you implement Full adder using half-adder? Explain the circuit diagram. [6] An adder is a digital logic circuit in electronics that implements addition

More information

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018

UNIVERSITY OF BOLTON SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 UNIVERSITY OF BOLTON [EES04] SCHOOL OF ENGINEERING BENG (HONS) ELECTRICAL & ELECTRONICS ENGINEERING SEMESTER TWO EXAMINATION 2017/2018 INTERMEDIATE DIGITAL ELECTRONICS AND COMMUNICATIONS MODULE NO: EEE5002

More information

0 0 Q Q Q Q

0 0 Q Q Q Q Question 1) Flip Flops and Counters (15 points) a) Fill in the truth table for a JK flip flop. Use Q or Q to denote the previous value of Q and Q. (6 pts) J K CLK Q Q Q Q 1 1 1 1 1 1 Q Q b) In Figure 1a

More information

Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. Digital Logic

Computer Systems and Networks. ECPE 170 Jeff Shafer University of the Pacific. Digital Logic ECPE 170 Jeff Shafer University of the Pacific Digital Logic 2 Homework Review 2.33(d) Convert 26.625 to IEEE 754 single precision floa9ng point: Format requirements for single precision (32 bit total

More information

Function Table of an Odd-Parity Generator Circuit

Function Table of an Odd-Parity Generator Circuit Implementation of an Odd-Parity Generator Circuit The first step in implementing any circuit is to represent its operation in terms of a Truth or Function table. The function table for an 8-bit data as

More information

S-[F] NPW-02 June All Syllabus B.Sc. [Electronics] Ist Year Semester-I & II.doc - 1 -

S-[F] NPW-02 June All Syllabus B.Sc. [Electronics] Ist Year Semester-I & II.doc - 1 - - 1 - - 2 - - 3 - DR. BABASAHEB AMBEDKAR MARATHWADA UNIVERSITY, AURANGABAD SYLLABUS of B.Sc. FIRST & SECOND SEMESTER [ELECTRONICS (OPTIONAL)] {Effective from June- 2013 onwards} - 4 - B.Sc. Electronics

More information

Exercises: Fundamentals of Computer Engineering 1 PAGE: 1

Exercises: Fundamentals of Computer Engineering 1 PAGE: 1 Exercises: Fundamentals of Computer Engineering PAGE: Exercise Minimise the following using the laws of Boolean algebra. f = a + ab + ab.2 f ( ) ( ) ( ) 2 = c bd + bd + ac b + d + cd a + b + ad( b + c)

More information

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits

Module 4: Design and Analysis of Combinational Circuits 1. Module-4. Design and Analysis of Combinational Circuits 1 Module-4 Design and Analysis of Combinational Circuits 4.1 Motivation: This topic develops the fundamental understanding and design of adder, substractor, code converter multiplexer, demultiplexer etc

More information

Classification of Digital Circuits

Classification of Digital Circuits Classification of Digital Circuits Combinational logic circuits. Output depends only on present input. Sequential circuits. Output depends on present input and present state of the circuit. Combinational

More information

Preface... iii. Chapter 1: Diodes and Circuits... 1

Preface... iii. Chapter 1: Diodes and Circuits... 1 Table of Contents Preface... iii Chapter 1: Diodes and Circuits... 1 1.1 Introduction... 1 1.2 Structure of an Atom... 2 1.3 Classification of Solid Materials on the Basis of Conductivity... 2 1.4 Atomic

More information

COUNTERS AND REGISTERS

COUNTERS AND REGISTERS H P T E R 7 OUNTERS N REGISTERS OUTLINE Part 7- synchronous (Ripple) ounters 7-2 Propagation elay in Ripple ounters 7-3 Synchronous (Parallel) ounters 7-4 ounters with MO Numbers 6 2 N 7-5 Synchronous

More information

Spec. Instructor: Center

Spec. Instructor: Center PDHonline Course E379 (5 PDH) Digital Logic Circuits Volume III Spec ial Logic Circuits Instructor: Lee Layton, P.E 2012 PDH Online PDH Center 5272 Meadow Estatess Drive Fairfax, VA 22030-6658 Phone &

More information

4. Forward bias of a silicon P-N junction will produce a barrier voltage of approximately how many volts? A. 0.2 B. 0.3 C. 0.7 D. 0.

4. Forward bias of a silicon P-N junction will produce a barrier voltage of approximately how many volts? A. 0.2 B. 0.3 C. 0.7 D. 0. 1. The dc current through each diode in a bridge rectifier equals A. the load current B. half the dc load current C. twice the dc load current D. one-fourth the dc load current 2. When matching polarity

More information

EXPERIMENT 12: DIGITAL LOGIC CIRCUITS

EXPERIMENT 12: DIGITAL LOGIC CIRCUITS EXPERIMENT 12: DIGITAL LOGIC CIRCUITS The purpose of this experiment is to gain some experience in the use of digital logic circuits. These circuits are used extensively in computers and all types of electronic

More information

Digital Electronic Concepts

Digital Electronic Concepts Western Technical College 10662137 Digital Electronic Concepts Course Outcome Summary Course Information Description Career Cluster Instructional Level Total Credits 4.00 Total Hours 108.00 This course

More information

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design

COMBINATIONAL and SEQUENTIAL LOGIC CIRCUITS Hardware implementation and software design PH-315 COMINATIONAL and SEUENTIAL LOGIC CIRCUITS Hardware implementation and software design A La Rosa I PURPOSE: To familiarize with combinational and sequential logic circuits Combinational circuits

More information

Chapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1

Chapter 4: FLIP FLOPS. (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT EE 202 : DIGITAL ELECTRONICS 1 Chapter 4: FLIP FLOPS (Sequential Circuits) By: Siti Sabariah Hj. Salihin ELECTRICAL ENGINEERING DEPARTMENT 1 CHAPTER 4 : FLIP FLOPS Programme Learning Outcomes, PLO Upon completion of the programme, graduates

More information

Lecture 3: Logic circuit. Combinational circuit and sequential circuit

Lecture 3: Logic circuit. Combinational circuit and sequential circuit Lecture 3: Logic circuit Combinational circuit and sequential circuit TRAN THI HONG HONG@IS.NAIST.JP Content Lecture : Computer organization and performance evaluation metrics Lecture 2: Processor architecture

More information

Electronic Circuits EE359A

Electronic Circuits EE359A Electronic Circuits EE359A Bruce McNair B206 bmcnair@stevens.edu 201-216-5549 1 Memory and Advanced Digital Circuits - 2 Chapter 11 2 Figure 11.1 (a) Basic latch. (b) The latch with the feedback loop opened.

More information

Chapter 3 Digital Logic Structures

Chapter 3 Digital Logic Structures Chapter 3 Digital Logic Structures Transistor: Building Block of Computers Microprocessors contain millions of transistors Intel Pentium 4 (2000): 48 million IBM PowerPC 750FX (2002): 38 million IBM/Apple

More information

Computer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University

Computer Architecture: Part II. First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Computer Architecture: Part II First Semester 2013 Department of Computer Science Faculty of Science Chiang Mai University Outline Combinational Circuits Flips Flops Flops Sequential Circuits 204231: Computer

More information

Time: 3 hours Max. Marks: 70 Answer any FIVE questions All questions carry equal marks

Time: 3 hours Max. Marks: 70 Answer any FIVE questions All questions carry equal marks Code: 9A02401 PRINCIPLES OF ELECTRICAL ENGINEERING (Common to EIE, E.Con.E, ECE & ECC) Time: 3 hours Max. Marks: 70 1 In a series RLC circuit, R = 5 Ω, L = 1 H and C = 1 F. A dc v ltage f 20 V is applied

More information

EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics

EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics EECS-140/141 Introduction to Digital Logic Design Lecture 7:Sequential Logic Basics I. OVERVIEW I.A Combinational vs. Sequential Logic Combinational Logic (everything so far): Outputs depend entirely on

More information

2 Building Blocks. There is often the need to compare two binary values.

2 Building Blocks. There is often the need to compare two binary values. 2 Building Blocks 2.1 Comparators There is often the need to compare two binary values. This is done using a comparator. A comparator determines whether binary values A and B are: 1. A = B 2. A < B 3.

More information

Digital Electronics. A. I can list five basic safety rules for electronics. B. I can properly display large and small numbers in proper notation,

Digital Electronics. A. I can list five basic safety rules for electronics. B. I can properly display large and small numbers in proper notation, St. Michael Albertville High School Teacher: Scott Danielson September 2016 Content Skills Learning Targets Standards Assessment Resources & Technology CEQ: WHAT MAKES DIGITAL ELECTRONICS SO IMPORTANT

More information

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam

CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam CS302 Digital Logic Design Solved Objective Midterm Papers For Preparation of Midterm Exam MIDTERM EXAMINATION 2011 (October-November) Q-21 Draw function table of a half adder circuit? (2) Answer: - Page

More information

Serial Addition. Lecture 29 1

Serial Addition. Lecture 29 1 Serial Addition Operations in digital computers are usually done in parallel because that is a faster mode of operation. Serial operations are slower because a datapath operation takes several clock cycles,

More information

Digital Electronics. Functions of Combinational Logic

Digital Electronics. Functions of Combinational Logic Digital Electronics Functions of Combinational Logic Half-dder Basic rules of binary addition are performed by a half adder, which has two binary inputs ( and B) and two binary outputs (Carry out and Sum).

More information

Final Project Report 4-bit ALU Design

Final Project Report 4-bit ALU Design ECE 467 Final Project Report 4-bit ALU Design Fall 2013 Kai Zhao Aswin Gonzalez Sepideh Roghanchi Soroush Khaleghi Part 1) Final ALU Design: There are 6 different functions implemented in this ALU: 1)

More information

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI

MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI MAHALAKSHMI ENGINEERING COLLEGE TIRUCHIRAPALLI 6 DEPARTMENT: ECE QUESTION BANK SUBJECT NAME: DIGITAL SYSTEM DESIGN SEMESTER III SUBJECT CODE: EC UNIT : Design of Combinational Circuits PART -A ( Marks).

More information

High Speed Binary Counters Based on Wallace Tree Multiplier in VHDL

High Speed Binary Counters Based on Wallace Tree Multiplier in VHDL High Speed Binary Counters Based on Wallace Tree Multiplier in VHDL E.Sangeetha 1 ASP and D.Tharaliga 2 Department of Electronics and Communication Engineering, Tagore College of Engineering and Technology,

More information

NORTH MAHARASHTRA UNIVERSITY, JALGAON

NORTH MAHARASHTRA UNIVERSITY, JALGAON , JALGAON Syllabus for F.Y.B.Sc. Semester I and II ELECTRONICS (w. e. f. June 2012) F.Y. B. Sc. Subject Electronics Syllabus Structure Semester Code Title Number of Lectures ELE-111 Paper I : Analog Electronics

More information

Module-20 Shift Registers

Module-20 Shift Registers 1 Module-20 Shift Registers 1. Introduction 2. Types of shift registers 2.1 Serial In Serial Out (SISO) register 2.2 Serial In Parallel Out (SIPO) register 2.3 Parallel In Parallel Out (PIPO) register

More information

Electronic Devices & Circuit and Digital Electronics

Electronic Devices & Circuit and Digital Electronics QUESTION BANK Electronic Devices & Circuit and Digital Electronics 1. Consider the following four statement i) In the 2 s complement representation, negative numbers are stored in sign magnitude form ii)

More information

NORTH MAHARASHTRA UNIVERSITY. F.Y. B. Sc. Electronics. Syllabus. Wieth effect from june2015

NORTH MAHARASHTRA UNIVERSITY. F.Y. B. Sc. Electronics. Syllabus. Wieth effect from june2015 Syllabus Wieth effect from june2015 Paper- I, Semester I ELE-111: Analog Electronics I Unit- I:Introduction to Basic Circuit Components Definition and unit, Circuit Symbol, Working Principle, Classification

More information

B.C.A 2017 DIGITAL ELECTRONICS BCA104T MODULE SPECIFICATION SHEET. Course Outline

B.C.A 2017 DIGITAL ELECTRONICS BCA104T MODULE SPECIFICATION SHEET. Course Outline Course Outline B.C.A 2017 DIGITAL ELECTRONICS BCA104T MODULE SPECIFICATION SHEET The purpose of the course is to teach principles of digital electronics. This course covers varieties of topics including

More information

Lecture 02: Digital Logic Review

Lecture 02: Digital Logic Review CENG 3420 Lecture 02: Digital Logic Review Bei Yu byu@cse.cuhk.edu.hk CENG3420 L02 Digital Logic. 1 Spring 2017 Review: Major Components of a Computer CENG3420 L02 Digital Logic. 2 Spring 2017 Review:

More information

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011

Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7/11/2011 Chapter 5 Sequential Logic Circuits Part II Hiroaki Kobayashi 7//2 Ver. 72 7//2 Computer Engineering What is a Sequential Circuit? A circuit consists of a combinational logic circuit and internal memory

More information

CHAPTER 6 DIGITAL INSTRUMENTS

CHAPTER 6 DIGITAL INSTRUMENTS CHAPTER 6 DIGITAL INSTRUMENTS 1 LECTURE CONTENTS 6.1 Logic Gates 6.2 Digital Instruments 6.3 Analog to Digital Converter 6.4 Electronic Counter 6.6 Digital Multimeters 2 6.1 Logic Gates 3 AND Gate The

More information

COURSE LEARNING OUTCOMES AND OBJECTIVES

COURSE LEARNING OUTCOMES AND OBJECTIVES COURSE LEARNING OUTCOMES AND OBJECTIVES A student who successfully fulfills the course requirements will have demonstrated: 1. an ability to analyze and design CMOS logic gates 1-1. convert numbers from

More information

FIRSTRANKER. 1. (a) What are the advantages of the adjustable voltage regulators over the fixed

FIRSTRANKER. 1. (a) What are the advantages of the adjustable voltage regulators over the fixed Code No: 07A51102 R07 Set No. 2 1. (a) What are the advantages of the adjustable voltage regulators over the fixed voltage regulators. (b) Differentiate betweenan integrator and a differentiator. [8+8]

More information

Design and build a prototype digital motor controller with the following features:

Design and build a prototype digital motor controller with the following features: Nov 3, 26 Project Digital Motor Controller Tom Kovacsi Andrew Rossbach Arnold Stadlin Start: Nov 7, 26 Project Scope Design and build a prototype digital motor controller with the following features:.

More information

Paper No. Name of the Paper Theory marks Practical marks Periods per week Semester-I I Semiconductor

Paper No. Name of the Paper Theory marks Practical marks Periods per week Semester-I I Semiconductor Swami Ramanand Teerth Marathwada University, Nanded B. Sc. First Year Electronics Syllabus Semester system (To be implemented from Academic Year 2009-10) Name of the Theory marks Practical marks Periods

More information

Asst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02)

Asst. Prof. Thavatchai Tayjasanant, PhD. Power System Research Lab 12 th Floor, Building 4 Tel: (02) 2145230 Aircraft Electricity and Electronics Asst. Prof. Thavatchai Tayjasanant, PhD Email: taytaycu@gmail.com aycu@g a co Power System Research Lab 12 th Floor, Building 4 Tel: (02) 218-6527 1 Chapter

More information

1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.

1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e. Name: Multiple Choice 1.) If a 3 input NOR gate has eight input possibilities, how many of those possibilities result in a HIGH output? (a.) 1 (b.) 2 (c.) 3 (d.) 7 (e.) 8 2.) The output of an OR gate with

More information

ECOM 4311 Digital System Design using VHDL. Chapter 9 Sequential Circuit Design: Practice

ECOM 4311 Digital System Design using VHDL. Chapter 9 Sequential Circuit Design: Practice ECOM 4311 Digital System Design using VHDL Chapter 9 Sequential Circuit Design: Practice Outline 1. Poor design practice and remedy 2. More counters 3. Register as fast temporary storage 4. Pipelined circuit

More information

6.1 In this section, you will design (but NOT build) a circuit with 4 inputs,

6.1 In this section, you will design (but NOT build) a circuit with 4 inputs, EE 2449 Experiment 6 Jack Levine and Nancy Warter-Perez //208 CALIFORNIA STATE UNIVERSITY LOS ANGELES Department of Electrical and Computer Engineering EE-2449 Digital Logic Lab EXPERIMENT 6 COMBINATIONAL

More information

Unit 3. Logic Design

Unit 3. Logic Design EE 2: Digital Logic Circuit Design Dr Radwan E Abdel-Aal, COE Logic and Computer Design Fundamentals Unit 3 Chapter Combinational 3 Combinational Logic Logic Design - Introduction to Analysis & Design

More information

Thursday 5 June 2014 Afternoon

Thursday 5 June 2014 Afternoon Thursday 5 June 214 Afternoon A2 GCE ELECTRONICS F614/1 Electronic Control Systems *3119659* Candidates answer on the Question Paper. OCR supplied materials: None Other materials required: Scientific calculator

More information

Lab #10: Finite State Machine Design

Lab #10: Finite State Machine Design Lab #10: Finite State Machine Design Zack Mattis Lab: 3/2/17 Report: 3/14/17 Partner: Brendan Schuster Purpose In this lab, a finite state machine was designed and fully implemented onto a protoboard utilizing

More information

Chapter 1: Digital logic

Chapter 1: Digital logic Chapter 1: Digital logic I. Overview In PHYS 252, you learned the essentials of circuit analysis, including the concepts of impedance, amplification, feedback and frequency analysis. Most of the circuits

More information

PROPOSED SCHEME OF COURSE WORK

PROPOSED SCHEME OF COURSE WORK PROPOSED SCHEME OF COURSE WORK Course Details: Course Title : LINEAR AND DIGITAL IC APPLICATIONS Course Code : 13EC1146 L T P C : 4 0 0 3 Program: : B.Tech. Specialization: : Electrical and Electronics

More information

GOVERNMENT OF KARNATAKA KARNATAKA STATE PRE-UNIVERSITY EDUCATION EXAMINATION BOARD II YEAR PUC EXAMINATION JULY-2012 SCHEME OF VALUATION

GOVERNMENT OF KARNATAKA KARNATAKA STATE PRE-UNIVERSITY EDUCATION EXAMINATION BOARD II YEAR PUC EXAMINATION JULY-2012 SCHEME OF VALUATION GOVERNMENT OF KARNATAKA KARNATAKA STATE PRE-UNIVERSITY EDUCATION EXAMINATION BOARD II YEAR PUC EXAMINATION JULY-0 SCHEME OF VALUATION Subject Code: 40 Subject: PART - A 0. Which region of the transistor

More information

CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT

CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER 3 BASIC & COMBINATIONAL LOGIC CIRCUIT CHAPTER CONTENTS 3.1 Introduction to Basic Gates 3.2 Analysing A Combinational Logic Circuit 3.3 Design A Combinational Logic Circuit From Boolean Expression

More information

Sequential Logic Circuits

Sequential Logic Circuits Exercise 2 Sequential Logic Circuits 1 - Introduction Goal of the exercise The goals of this exercise are: - verify the behavior of simple sequential logic circuits; - measure the dynamic parameters of

More information