Computer Architecture and Organization:

Transcription

1 Computer Architecture and Organization: L03: Register transfer and System Bus By: A. H. Abdul Hafez 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

2 Outlines 1. Registers 2. Micro-operation 3. Register transfer 4. Simultaneous Register Transfers 5. Illegal Simultaneous Register Transfers 6. Bus transfer 7. Bus system 8. Constructing bus system using multiplexers 9. Constructing bus system using three-state buffers 10. Memory transfer 11. Arithmetic microoperation 12. Full adder 13. Four bit parallel adder 14. End 2 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

3 Registers A register is a group of flip flops, each of which is capable of storing one bit of information. Clock inputs triggers all flip flops at the positive (rising) edge of each pulse. Clear input (low active) reset the all outputs to 0s. It must be 1 in normal operation. Four bits register 3 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

4 Register with parallel load Transferring new information into the register is called loading the register. If all the bits of register are loaded simultaneously with a common clock pulse, the loading is called parallel load. To leave the content of the register unchanged, the input must held constant or the clock should be prohibited. The additional circuits play the role of MUX whose outputs drive data to the register either from the data bus or from the output of the register it self. 4 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

5 Shift register A register that is capable of shifting the binary data from its current cell to a neighbor cell. The logical configuration is a chain of flip flops. The output of one flip flop is connected to the input of the next flip flop. All flip flops are connected to a common clock. 5 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

6 Registers Single Flip-Flop can save information of 1 bit. To save n-bit, we need n Flip Flops connected together. We have then n bits register. Shift Register is a group of Flip Flops connected together to save and shift n-bit data. Different types of Shift Registers are available: 6 Computer Organizatrion - Dr. Abdul Hafez, ATRI 12-Oct-16

7 Microoperations The operations that are performed on the data stored in registers are called microoperations. Examples of microoperations are: transfer, shift, clear and load. Digital modulus ( Ex: microprocessor) are best defined by the registers they contain and the operations that performed on the data stored in them. Microoperations are the basis for Microprocessors. An instruction is fetched from memory, decoded and executed by performing a sequence of microoperations. A microprocessor performs the microoperations in order to realize the instruction. 7 Computer Organizatrion - Dr. Abdul Hafez, ATRI 12-Oct-16

8 Hardware organization Internal hardware organization of a computer is best defined by: 1. The set of registers. 2. The sequence of Microoperations performed on these registers. 3. The control that initiates the sequence of Microoperations. 8 Computer Organizatrion - Dr. Abdul Hafez, ATRI 12-Oct-16

9 Register Representation Computer registers are designated by capital letters (sometimes followed by numerals) to define the function of the register. Examples: R1 processor register, PC Program Counter, AC Accumulator. In diagrams, the registers are represented by rectangular box with the name of the register inside as shown in the Figure. The individual flip-flops (bits) are distinguished by writing the location number of the bit as in (b) or ( c) and (d) in the figure. R1 (a) Register R (b) Showing individual bits R2 PC (H) PC (L) (c) Numbering of bits (d) Divided into two parts 9 Computer Organizatrion - Dr. Abdul Hafez, ATRI 12-Oct-16

10 Basic Symbols for Register Transfers Symbol Description Examples Letters (and numerals) Parentheses ( ) Arrow Comma, Denotes a register Denotes a part of a Register Denotes transfer of information Separates two microopeartions MAR, R2 R2(0-7), R2(L) R2 R1 R2 R1, R1 R2 10 Computer Organizatrion - Dr. Abdul Hafez, ATRI 12-Oct-16

11 Register Transfer R2 R1 denotes a transfer of the content (copy) of register R1 (source register) into register R2 (destination register). P: R2 R1 When condition P occurs, the contents of register R1 are copied into register R2. Alternatively, we can say if (P=1) then ( R2 R1 ). P is a control signal generated in the control circuit. Every statement written in a register transfer notation implies a hardware construction for implementing the transfer. The circuit diagram for the register transfer P: R2 R1 is shown below. Control circuit P- Load R2 Clock n R1 Transfer occurs (a) block diagram here 11 Computer Organizatrion - Dr. Abdul Hafez, ATRI (b) Timing diagram 12-Oct-16

12 Simultaneous Register Transfers T: R2 R1, R3 R1 When signal T is asserted, the contents of R1 are copied into both registers R2 and R3. Note that the order in which the statement is written does not matter. T: R2 R1, R4 R3 two registers (R2 and R4) are loaded simultaneously from different sources. R2 R3 R2 R1 T T R1 T R4 R3 T: R2 R1, R3 R1 T: R2 R1, R4 R3 12 Computer Organizatrion - Dr. Abdul Hafez, ATRI 12-Oct-16

13 Illegal Simultaneous Transfers Example of an illegal operation is shown below, since A is loaded with two different values simultaneously. Solution 0 A MU X 1 P V Q Q P: A B Q: A C B C Register A can receive data from more than one source, depending on the control signal asserted. A multiplexer is used to determine the data to be loaded, although tristate buffers could also have been used. 13 Computer Organizatrion - Dr. Abdul Hafez, ATRI 12-Oct-16

14 Bus Transfers A typical digital computer has many registers, and paths (lines) must be provided to transfer information (data) from one register to another. For n registers system, the number of wires will be excessive if separate lines are used between each register and all other registers in the system! R1 R2 R6 R3 R5 R4 To connect n items with direct connections, you need n(n-1)/2 connections. 14 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

15 Bus System A more efficient scheme for transferring information between registers in a multiple-register configuration is a common bus system. A bus system consists of a set of common lines, one for each bit of a register, through which binary information is transferred one at a time. Control signals determine which register is selected by the bus during each particular transfer. R1 R2 Common Bus R6 R3 R5 R4 To connect n items with bus connections, you need only n connections. 15 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

16 Constructing bus system using multiplexers The multiplexer selects one of the four registers as the source register. Control lines for the MUX are driven by external circuitry. The data is made available to all registers, but only one actually loads the data. Again, external hardware generates load signals for the four registers such that no more than one is active at any given time. The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement. When bus is included in the statement we write: BUS C, A BUS (however it is A C) P: A B Q: A C R: B D S: C A T: D C U: D B 16 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

17 4-line Common bus A 3 A S 0 S 1 A 1 A 0 4X1 MUX 3 4X1 MUX 2 4X1 MUX 1 4X1 MUX D 2 C 2 B 2 A 2 D 1 C 1 B 1 A 1 D 0 C 0 B 0 A 0 D 2 D 1 D 0 C 2 C 1 C 0 B 2 B 1 B 0 A 2 A 1 A Register D Register C Register B Register A Detail connection of the Bus system for 4 registers 17 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

18 In general, a bus system will multiplex k registres of n bit each to produce an n- line common bus. 1- The number of multiplexers needed to construct the bus is equal to n, the number of bits in each register. 2- The size of each multiplexer must be k x 1 since it multiplexes k data lines. # example: a common bus of 8 registers of 16 bits each requires 16 multiplexers, one for each line in the bus. Each MUX must have 8 input lines and three selector lines to multiplex one bit in the 8 registers. 18 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

19 Constructing bus system using three-state buffers A three-state gate is a digital circuit that exhibits three states. Two of the states are signals equivalent to logic 1 and 0 as in a conventional gate. The third state is called high impedance state The high impedance state behaves like an open circuit which means that the output is disconnected and does not have a logic significance. Normal Input A Control Input C Output Y=A if C=1 High-impedance if C=0 19 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

20 Bus lines Bit 3 Bit 2 Bit 1 Bit 0 S 0 S 1 2 X 4 Decoder S 0 S X 4 Decoder S 0 S X 4 Decoder S 0 S X 4 S Decoder 0 S D 3 C 3 B 3 A 3 D 2 C 2 B 2 A 2 D 1 C 1 B 1 A 1 D 0 C 0 B 0 A 0 D 3 D 2 D 1 D 0 C 3 C 2 C 1 C 0 B 3 B 2 B 1 B 0 A 3 A 2 A 1 A Register D Register C Register B Register A 4-line Bus system using three state-buffer 20 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

21 Memory Transfer Microprocessor DR Data lines Write Read Memory Unit Read: DR M[AR] Write: M[AR] DR Address lines Read operation Write operation 21 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

22 Main Types of Microoperations in Digital Computers 1. Register Transfer Microoperations transfer binary information from one register to another. 2. Arithmetic Microoperations perform arithmetic operations on numeric data stored in registers. 3. Logic Microoperations perform bit manipulation operations on (non-numeric) data stored in registers. 4. Shift Microoperations perform shift operations on data stored in registers. 22 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

23 Arithmetic Microoperations Symbolic Designation R3 R1 + R2 R3 R1 R2 R2 R 2 R2 R Description Contents of R1 plus R2 transferred to R3 Contents of R1 minus R2 transferred to R3 Complement of the contents of R2 (1 s complement) 2 s complement of the contents of R2 R3 R1 + R R1 plus the 2 s complement of R2 (subtraction) R1 R1 + 1 R1 R1-1 Increment the contents of R1 by one Decrement the contents of R1 by one 23 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

24 The full Adder Half Adder x y c s c = xy s = xy + x y = x y x y c s Full Adder x y c n-1 c n s x y c n-1 S c n 24 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

25 The full Adder The full adder accepts two input bits and an input carry and generates a sum output and an output carry A B C in C out CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

26 Four-bits parallel adder 26 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU

27 The end of the Lecture Thanks for your time Questions are welcome 27 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU