EC4205 Microprocessor and Microcontroller

Transcription

1 EC4205 Microprocessor and Microcontroller Webcast link: All announcement made through webpage: check back often Students are welcome outside the class (right after class) Dr. A. Islam Dept. of ECE BIT, Mesra, Ranchi Prepared and presented by Dr. A. Islam 1

2 EC4205 Lecture notes based on material From me, Prof. (Dr.) R. Sukesh Kumar and following text books: 1. Digital Computer Electronics, 2/e, by A. P. Malvino. 2. Microprocessor Architecture, Programming and Applications with 8085, by R. S. Gaonkar. 3. Microprocessor and Interfacing, Programming of Hardware, by D. Hall. 4. Microprocessor and Peripherals, by S. P. Chowdhury and S. Chowdhury. 5. INTEL 8086/8088 Microprocessor, Architecture, Programming, Design and Interfacing, 3/e, by B. S. Chhabra. 6. Microprocessor, Microcomputer and their Applications, 2/e, by A, K. Mukhopadhyay. 7. The Intel Microprocessors 8086/888, 80186/80188, 80286, 80386, 80486, Pentium and Pentium Pro processor architecture, programming and interfacing, 4/e, by B. B. Brey. 8. Microprocessors with applications in process control, by SI Ahson. 9. Microprocessors theory and applications: Intel and Motorola, by M. Rafiquzzaman. Use the material without violating copyright act involved with original books. Prepared and presented by Dr. A. Islam 2

3 Module-I: Outline 1. Revision of logic circuits with emphasis on control lines 2. SAP concepts with stress on timing diagrams 3. Microinstructions 4. Microprogramming 5. Variable machine cycle 6. Architecture of 8085 Processor 7. Functions of all signals 8. Bus concepts 9. Multiplexed and De-multiplexed Bus 10.Minimum system Prepared and presented by Dr. A. Islam 3

4 D latch using one 2- input multiplexer and two inverters is shown in Fig. 1.30(a) (Weste 3/e). The multiplexer can be constructed from a pair of transmission gates, as shown in the D latch illustrated in Fig. 1.30(b). Revision of logic circuits Prepared and presented by Dr. A. Islam 4

5 By combining two levelsensitive latches, one positive-sensitive and one negative- sensitive, we construct an edgetriggered flip-flop as shown in Figure 1.31(a-b). By convention, the first latch stage is called the master and the second is called the slave. Revision of logic circuits While CLK is low, the master negative-level-sensitive latch output (QM bar) follows the D input while the slave positive-level-sensitive latch holds the previous value. When the clock transitions from 0 to 1, the master latch ceases to sample the input and holds the D value at the time of the clock transition. The slave latch opens, passing the stored master value to the output of the slave latch (Q). The D input is blocked from affecting the output because the master is disconnected from the D input. Prepared and presented by Dr. A. Islam 5

6 Propagation delay time: t p represents the amount of time it takes for the o/p of a gate or FF to change states. For instance, if the data sheet of D FF indicates a t p of 10ns, it takes 10ns for Q to change states after D has been sampled by the clock edge. Setup time: t setup is the minimum length of time the data bit must be present before the clock edge hits. For instance, if the data sheet of a D- FF indicates a t setup of 15ns, the data bit to be stored must be at the D i/p at least 15ns before clock edge arrives; otherwise, the IC manufacturer does not guarantee correct sampling & storing. Hold time: t hold is the minimum length of time the data bit must be present after the clock edge has struck. For example, if t setup is 15ns and t hold is 5ns, the data bit has to be at the D i/p at least 15ns before the CLK edge arrives and held at least 5ns after the CLK edge hits. Prepared and presented by Dr. A. Islam 6

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9 Fig. 7.12(a)(Malvino) Edge triggered JK FF The R-C circuit in Fig 7.12(a)(Malvino) is high-pass filter that passes the high frequency component of the input signal to output because the reactance of a capacitor decreases with increasing frequency. At zero frequency the capacitor has infinite reactance and hence behaves as an open circuit. As the capacitor blocks constant (dc )input, C is called blocking capacitor. Response of this high-pass filter to a square wave is spike as shown in Fig 7.12(a)(Malvino). Prepared and presented by Dr. A. Islam 9

10 Fig. 2.14(Milman_Taub)low-pass RC circuit Fig. 2.18(c)(Milman_Taub)respose of low-pass RC circuit to square-wave The low-pass RC (or integrator) circuit of Fig. 2.14(Milman_Taub) cannot be used for edge triggering as its response to square-wave input is as shown in Fig. 2.18(c) (Milman_Taub) Prepared and presented by Dr. A. Islam 10

11 Race around condition and its remedy: In a JK- FF if we replace edgetriggered with a level triggered clock and clock goes high and J=k=1, the o/p will toggle. New o/ps are then fed back to i/p gates. After two propagation delay time, the o/p toggles again if the clock pulse remains high and once more, new o/ps return to the i/p gates. In this way, the o/p can toggle repeatedly as long as the clock pulse remains high. That means we get oscillations during +ve half of the clock and when the +ve clock pulse dies, the o/p is unpredictable. Toggling more than once during a clock cycle is called race around condition. Race around condition can be avoided by (a) By edge-trigging the JK-FF, (b) Using masterslave JK-FF and (c) making propagation delay greater than pulse width which is practically difficult because the propagation delay of ICs is very low. Prepared and presented by Dr. A. Islam 11