GOVERNMENT OF KARNATAKA KARNATAKA STATE PRE-UNIVERSITY EDUCATION EXAMINATION BOARD II YEAR PUC EXAMINATION JULY-2012 SCHEME OF VALUATION

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1 GOVERNMENT OF KARNATAKA KARNATAKA STATE PRE-UNIVERSITY EDUCATION EXAMINATION BOARD II YEAR PUC EXAMINATION JULY-0 SCHEME OF VALUATION Subject Code: 40 Subject: PART - A 0. Which region of the transistor is physically large? Collector. 0. What is the phase difference between input and output voltage of CC amplifier? 0º or 360º or no phase difference. 03. What happens to the gain stability on using negative feedback in amplifiers? Increases or improves. 04. What is the voltage gain of a buffer amplifier? or unity. 05. Between Hartley and Wien bridge oscillators, which is preferred for generating high frequency? Hartley. 06. Define critical frequency? The highest frequency that can be sent from a specific layer of the ionosphere back to earth. 07. What happens if m a is greater than one in AM? Distortion in AM wave or over modulation. 08. Name the logic gate which produces a high output, only when all its inputs are low. NAND or NOR or XNOR. 09. Convert Gray code (00) into binary. 0 () 0. Expand ISP. Internet Service Provider. PART - B. How are emitter base and collector base junctions biased in the active region? Emitter base junction is forward biased Collector base junction is reverse biased.. Calculate the mid band gain of an amplifier, if the gain at cutoff frequencies is A v = 7.07 x A v = Draw the frequency response curve of an amplifier with and without feedback. Without feed back With feedback

2 4. Distinguish between an amplifier and oscillator. Amplifier: Amplifies the signal Oscillator: Generates AC signal. 5. What is pre-emphasis and de-emphasis? Pre-emphasis: The process of raising or boosting the relative amplitude of the higher audio frequencies. This is done during modulation. De-emphasis: The process of attenuating higher audio frequencies by the amount by which they are boosted. This is done during demodulation. 6. An amplitude modulated wave has maximum and minimum amplitudes of 75V and 5V respectively. Calculate the amplitude of modulating signal. V m = (V max V min ) / V m = (75-5)/ = 50/ = 5V 7. Write any two advantages of FM over AM. FM has less adjacent channel interference less noise reception. OR Any two suitable advantages each mark. 8. Convert the given Boolean Expression Y = A + BC into canonical SOP form. Y = A + BC Y = A( B+ B)( C+ C) + ( A+ A) BC Y = ABC+ ABC+ ABC + ABC + A B C 9. Draw the logic diagram of EX-OR gate using basic gates and write the output Boolean Expression. Y = AB + AB 0. Distinguish between sequential and combinational logic circuits. Sequential logic circuits: In which the output depends on the previous o/p and the present i/ps. Combinational logic circuits: In which the o/p depends only on the present i/ps.. What is a half adder? Write its truth table. Half adder adds two binary digits at a time. Inputs Outputs A B Carry Sum

3 . What is cell site and cell splitting? Cell site: A low powered base station. Cell splitting: Division of larger cells into sub cells to increase capacity of cellular network. PART - C 3. The following readings were obtained while studying CE amplifier. Draw the frequency response curve and determine frequency bandwidth of the amplifier. Given; V i = 0 mv. f in Hz K 00 K 400 K 600 K Vo in volt Voltage gain AV = V0/Vi f in Hz K 00 K 400 K 600 K Vo in volt A V Band width BW = (f h f l ) = (400 k 00) = khz OR 3. The following readings are recorded in an OP-Amp subtractor experiment. Calculate the output voltage, consider all the resistances are equal. Sl. Input to the inverting Input to the non-inverting V 0 (V) terminal (V) terminal (V) V 0 = (V + - V - ) Where V + = input to non inverting terminal V - = input to inverting terminal Sl. ; V 0 = ( ) = 0.59 V Sl. ; V 0 = ( ) = 0.47 V Sl. 3 ; V 0 = ( ) = V 3 4

4 4. i) Mention any two comparisons of single and multistage amplifiers. ii) Draw the symbol and one application of phototransistor. 4 i) Sl. Single stage amplifier Multi stage amplifier 0. One transistor stage Many transistor stages 0. Gain is less Gain is more Any other compaision each mark ii) Symbol of photo transistor: Application: Used in optocoupler. Or any one application 5. The input and output voltages of an amplifier are 0 mv and 0 V respectively. If the gain with negative feedback is 80 and input resistance without feedback is.5 kω. Calculate the feedback fraction and input resistance after feedback. 4 A = V0/Vi = 0/(0 x 0-3 ) = 000 β = (A/A f -)/A = (000/80-)/000 =0.05 Z if = Z i (+Aβ) Z if =.5x0 3 (+000x0.05) = 8.75 kω 6. Write any three differences between an inverting and non-inverting amplifier. Write any two characteristics of ideal OP-AMP. 4 Differences: Sl. Inverting amplifier Non inverting amplifier 0 Output is 80 0 with i/p Output is in phase with i/p 0 A = -R f / R i A= ( + (R f / R )) 03 When R f = 0, then A = 0 When R f = 0, then A = Characteristics of ideal Op-Amp: The open loop voltage gain is infinity (Av = ). The input impedance is infinity (Zi = ). The output impedance is zero (Z 0 = 0). The bandwidth is infinite (BW = ). The common mode rejection ratio is infinity (CMRR = ). The slew rate is infinity (SR = ). Perfect balance i.e., the output voltage is zero when both the inputs are equal. Characteristics do not drift with temperature. Any two of the above, each carry mark 4

5 7. With a circuit diagram derive an expression for output voltage of an OP-AMP integrator. Draw the output waveform for square wave input. 4 Fig: Op-Amp integrator From the figure i f = i i....() i f = dq/dt = Cd(V 0 - V G )/dt = Cd(V 0 )/dt.() i i = (V G -V i )/R = -V i /R (3) Therefore, Cd(V 0 )/dt = -V i /R V0 = - Vi dt RC (Proper steps must be considered) 8. Determine the output voltage V o for the following circuit. 4 V =. V, V = 0.6 V and V 3 = -. V. V 0 = - [(R f /R )xv + (R f /R )xv +(R f /R 3 )xv 3 ] V 0 = - [(3k/k)x. + (3k/k)x0.6 + (3k/k)x(-.)] V 0 = - [ ] V 0 = -.85 V 9. Calculate the frequency of oscillation of Colpitt s oscillator where L= mh, C = 0.0µf and C = 0.µf. 4 f = π LC T C T = Where X 0 X 0.X 0 6 ( ) X0 C C C = (C C ) T + = x 0 F 5

6 9. f = 3 6 π x 0 x x0 ) (for substitution and simplifications marks) f = 53 khz 30. Draw the block diagram of superheterodyne AM receiver. Briefly explain the functions of each block. 4 RF stage: Used to select desired station. Mixer: Generates IF which is difference between local oscillator and RF signal. IF Stage: Increases the strength of IF signal Detector: Separates signal from IF. Power Amplifier: Increases strength of audio signal. Speaker: Converts AF signal into sound signal. 3. With a circuit diagram and truth table explain the working of DTL-NAND gate. ( Two inputs). 4 Truth table Inputs Output A B Y(Vout) DTL NAND Gate Ckt mark Table - mark Working When A = 0, B = 0, then D and D conducts, Q off, therefore Y(V out ) = A = 0, B =, then D conduct and D doesn t conducts, Q off, Y(V out ) = A =, B = 0, then D doesn t conducts and D conduct, Q off, Y(V out ) = A =, B =, then D and D doesn t conducts, Q on, therefore Y(V out ) = 0 PART - D 3. Draw the pin diagram of IC Describe how NOT, AND and OR gates are realized using IC 7400 experimentally 6 6

7 3 Aim: To construct & to study NOT, AND and OR gates using NAND gates Equipment & components: Digital IC trainer, IC 7400, connecting wires etc., Pin diagram of IC 7400 NOT Gate using NAND gate Truth table A Y 0 0 AND gate using NAND gates Truth table Inputs Output A B Y OR Gate using NAND gates Truth table Inputs Output A B Y Procedure: Connect in 7 to Gnd and pin 4 to V CC. Circuit connections are made for NOT gate. Verify truth table. Do the experiment for AND and OR gates. Result: NOT, AND & OR gates are constructed using NAND gates & their truth tables are verified. OR 7

8 3. Describe an experiment to study OP-AMP as an inverting amplifier with pin diagram. 6 V OT = -(R f xv i )/R i A VT = -R f /R i A VP = V 0 /V i Procedure: Connections are made as shown in the circuit diagram. Input voltage is set at suitable value, note down output voltage. Compare practical and theoretical gains. Result: Op-amp inverting amplifier is constructed and the gains are verified. 8

9 33a. Explain the working of NPN transistor 4 Emitter base junction is forward biased by supply V EE collector base junction is reverse biased by supply V CC. Width of depletion layers shown in fig. The negative terminal of V EE repels electrons in the n type emitter layer towards base layer. Since base is very thin and lightly doped a few electrons recombine with base layer constitute base current I B. Majority of electrons emitted in the emitter layer reach collector region constitute collector current I C. Therefore I E + E B = I C 33b. The transistor in CB mode has a current gain of 0.98, if the collector current is 9.5mA, calculate the emitter current I E = I C /α I E = (9.5x0-3 )/0.98 =9.69 ma 34. Draw the single stage CE amplifier with input and output waveforms. Mention steps involved to obtain DC and AC equivalent circuit. 6 CE amplifier DC equivalent circuit: Reduce all AC sources to zero. Open all the capacitors AC equivalent circuit: Reduce all DC sources to zero. Short all the capacitors 9

10 35a. With a circuit diagram explain the working of a dual input unbalanced output differential amplifier. 4 Fig. Dual input unbalanced output Input is applied to both the input terminals output is taken across only one collector terminals. Output voltage v o is in phase with input V in and is out of phase with V in. If same signal (magnitude and phase) applied to both the input then the output is zero. Expression for output voltage is given by RC( vin vin Vo = ) re 35b. If the voltage gain of an amplifier is 00, express in decibel. Gain in db = 0 log 0 A v = 0 log 0 00 = 0 x = 40 db 36a. With the circuit diagram, frequency expression, explain working of a RC phase shift oscillator. 4 f = π RC 6 OR f = 0.065/RC 0

11 36a. Op-amp produces a phase shift of 80 0 degrees and feed back network consists of 3 RC sections produces a total phase shift of Therefore overall phase shift of is produced. The gain of feedback network, β = /9 to get oscillations the gain of amplifier (A V ) must be at least equal to 9. 36b. If the gain of the amplifier is 00, calculate feedback factor to meet Barkhausen criteria for obtaining sustained oscillations in an oscillator. For sustained oscillations, A β = β = / A = /00 = a. Derive an expression for instantaneous voltage of AM wave 4 Signal is represented by Carrier is represented by υ m = V m sinω m t υ c = V c sinω c t Amplitude of AM wave is given by A = V C + V m sinω m t A = V C (+ V m / V C sinω m t) = V C (+ m a sinω m t) AM wave is given by υ AM = A sinω C t υ AM = V C (+ m a sinω m t) sinω C t.() ().(3)..(4) m V (cosω υ AM = V c sinω c t + a c c m - ω ) t m a V c (cosω c + ω m ) t 37b. Calculate the length of antena required if the transmission signal is MHz. L = C/4f where C = velocity of light L = 3x0 8 /4xx0 6 = 75 m 38a. Explain the working of JK flip-flop with block diagram and write its truth table. 4 Truth Table Block diagram of JK Flip-flop mark Inputs CLK J K Q Outputs Q Conditions X 0 0 No Change Hold 0 0 Reset 0 0 Set Toggle Toggle mark

12 38a Working: Hold: When J = K = 0, CLK = X, then Q and Q doesn t change. Reset: When J = 0, K =, CLK =, then Q = 0 Set: When J =, K = 0, CLK =, then Q = Toggle: When J = K =, CLK =, then Q toggles 38b. What is race around condition? Name the flip-flop in which this condition is eliminated. Toggling of the output more than once during a single clock pulse is called race around condition In JK Master slave flip-flop race around condition is eliminated 39a. Simplify using K-Map and realize the simplified expression using NAND gates. Y = m(0,, 3, 4, 6, 8, 0,,, 4). N = b. What are weighted codes? Give an example. Weighted code is a binary cods in which every bit has position value. Example for weighted codes: 84, 4, 54, 5 (any one code) 40a. Draw the block diagram of monochrome TV receiver. 4 4 Block diagram of monochrome TV receiver 40b. Write any two limitations of . Limitations of is not secure. Virus can enter the computer of receiver. Unwanted mails reach mail box. (OR Any two acceptable limitations each carry mark) ***** s * h * i * v * a * s * h * a *n * k * a * r *** u * m * a * k * a * n * t * h *****

GOVERNMENT OF KARNATAKA KARNATAKA STATE PRE-UNIVERSITY EDUCATION EXAMINATION BOARD II YEAR PUC EXAMINATION MARCH-2012 SCHEME OF VALUATION

GOVERNMENT OF KARNATAKA KARNATAKA STATE PRE-UNIVERSITY EDUCATION EXAMINATION BOARD II YEAR PUC EXAMINATION MARCH-0 SCHEME OF VALUATION Subject Code: 0 Subject: Qn. PART - A 0. Which is the largest of three