Computer Architecture and Organization: L08: Design Control Lines

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1 Computer Architecture and Organization: L08: Design Control Lines By: A. H. Abdul Hafez 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU December 20, 2016

2 Outlines 1. Simple example: revision to bus system 2. Registers and Memory Control lines circuits 1. Design of TR and AR registers 2. Design of memory read and write lines 3. Common bus selection lines 3. Accumulator logic design 1. AC control lines 2. Adder logic design 4. End 2 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU December 20, 2016

3 3 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU December 20, 2016

4 Fetch Table (5-6) Control Functions and Microoperations for the basic computer (Mano computer) R T0: R T1: AR PC IR M[AR], PC PC + 1 Decode R T2: D0.D7 IR (12-14), I IR (15), AR IR (0-11) Indirect D 7 IT3: AR M[AR] Interrupt T0 T1 T2 IEN (FGI + FGO): R 1 RT0: Memory Reference AND D 0 T4: D 0 T5: ADD D 1 T4: D 1 T5: LDA D 2 T4: D 2 T5: AR 0, TR PC RT1: M[AR] TR, PC 0 RT2: PC PC + 1, IEN 0, R 0, SC 0 DR M[AR] AC AC ^ DR, SC 0 DR M[AR] AC AC ^ DR, E Cout, SC 0 DR M[AR] AC DR, SC 0 STA D 3 T4: M[AR] AC, SC 0 BUN D 4 T4: PC AR, SC 0 BSA D 5 T4: D 5 T5: ISZ D 6 T4: D 6 T5: D 6 T6: M[AR] PC, AR AR+1 PC AR, SC 0 DR M[AR] DR DR + 1 M[AR] DR, if DR=0 then PC PC + 1 Register Reference D7 I T3 = r IR( I ) = Bi [bit in IR (0-11) that specifies the operation] r: SC 0 CLA rb 11 : AC 0 CLE rb 10 : E 0 CMA rb 9 : AC AC CME rb 8 : E E CIR rb 7 : AC shr AC, AC(15) E, E AC (0) CIL rb 6 : AC shl AC, AC(0) E, E AC (15) INC rb 5 : AC AC+1 SPA rb 4 : If (AC (15)=0) then (PC PC+1) SNA rb 3 : If (AC (15)=1) then (PC PC+1) SZA rb 2 : If (AC =0) then (PC PC+1) SZE rb 1 : If (E=0) then (PC PC+1) HLT rb 0 : S 0 (S is a start-stop flip-flop) Input-output D7 I T3 =p (common for all input-output instructions) IR( I ) = Bi [bit in IR (6-11) that specifies the instructions] p: SC 0 INP pb 11 : AC(0-7) INPR, FGI 0 OUT pb 10 : OUTR AC (0-7), FGO 0 SKI pb 9 : if (FGI=1) then (PC PC + 1) SKO pb 8 : if (FGO=1) then (PC PC + 1) ION pb 7 : IEN 1 IOF pb 6 : IEN 0 4

5 Design of Basic Computer The proposed basic computer consists of the following hardware components: 1- A memory unit with 4096 words of 16 bits each. 2- Nine registers : AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC. 3- Seven Flip Flops: I, S, E, R, IEN, FGI, and FGO. 4- Two decoders: 3-to-8 op-code decoder and 4-to-16 timing decoder bit common bus. 6- Control logic gates. 7- Adder and logic circuit connected to the input of the accumulator. December 20, 2016 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU 5

...... S E R IEN FGI FGO DR instruction register (IR) 15 14 13 12 11-0 AC 3x8 decoder 7 6 5 4 3 2 1 0 D0 I

6 S E R IEN FGI FGO DR instruction register (IR) AC 3x8 decoder D0 I D7 T15 Control logic gates x6 decoder T0 4-bit Sequence Counter (SC) (CLR) Clock (INR) 6

7 Control Lines: Simple Example The multiplexer selects one of the four registers as the source register. Control lines for the MUX are driven by external circuitry. The data is made available to all registers, but only one actually loads the data. Again, external hardware generates load signals for the four registers such that no more than one is active at any given time. The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement. When bus is included in the statement we write: BUS C, A BUS (however it is A C) P: A B Q: A C R: B D S: C A T: D C U: D B 7 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU December 20, 2016

8 Registers and Memory Control lines circuits Note: To design the control circuit for any register or memory input control lines, we have to scan table (5-6) to find the required control functions for each control line. Ex: Design of TR After the scanning of table (5-6), TR is modified only by the microoperation RTo: TR PC, So the control circuit will be From Bus 12 TR 12 To the Bus LD R To CLK 8

9 Ex: Design of AR register Scan table (5-6) for the transfer statements that change the content of AR: R T0: AR PC R T2: AR IR(0-11) D 7IT3: AR M[AR] LD (AR) LD (AR) LD (AR) LD(AR)= R T0+R T2+D 7IT3 RT0: AR 0 D5T4: AR AR+1 CLR (AR) INR (AR) D 7 I T3 T2 From bus 1 2 AR LD INR CLR 1 2 to bus clock R T0 D5 T4 9

10 Ex: Design of Memory Read and Write control circuits Scanning the table, lead to the control functions for the Read and Write memory input lines: Read= R T 1 +D 7 IT 3 +(D 0 +D 1 +D 2 +D 6 ) T 4 Write= RT 1 +D 3 T 4 +D 5 T 4 +D 6 T 6 Memory Do D1 D2 D6 R T1 D 7 I T3 Read Write R T1 D3 T4 D5 T4 D6 T6 T4 10

11 Control circuit of single Flip Flop Ex: For the IEN Flip Flop, table 5-6 shows that IEN may change as a result of the instructions: ION, IOF, and is reset at the end of the interrupt cycle. The control functions and microoperations are: pb7: IEN 1 pb6: IEN 0 RT2: IEN 0 ION instruction IOF instruction ION instruction at the end of the interrupt cycle D'7 I T3 p B7 J SET Q J KQ(t+1) Clock IEN B6 R K CLR Q T2 11

12 Control of Common Bus Encoder for Bus Selection : Table. 5-6 S0 = x1 + x3 + x5 + x7 S1 = x2 + x3 + x6 + x7 S2 = x4 + x5 + x6 + x7 x1 = 1 : D T 4 D T 5 Control Function : x2 = 1 : Bus AR 4 5 : PC : PC AR AR Bus PC x D T D T5 x1 = 1 corresponds to the bus connection of AR as a source x 1 x 2 x 3 x 4 x 5 x 6 x 7 Encoder So S1 S2 Multiplexer Bus Select Input x7 = 1 : Bus Memory Same as Memory Read Control Function : x 7 R' T1 D7 ' IT3 ( D0 D1 D2 D3 ) T 4 12

13 Design of Accumulator Logic Circuit The circuits associated with the AC register are shown in the Figure below. The Adder has three inputs: one set of 16-bit from the output of the accumulator. Another set of 16-bit comes from the DR register. A third set of 8-bit comes from the INPR. The AC is provided with three control lines: LD, INR, and CLR. 16 From DR From INPR 16 8 Adder and logic circuit Accumulator register (AC) To Bus LD INR CLR Clock Control gates 13

14 Design of AC Register Search table 5-6 for the statements that change the content of AC. The statements, their control functions and the corresponding logic circuit are shown below. From adder and logic AC To Bus D0 AND LD INR CLR Clock D T 0 D T 1 2 pb rb rb rb rb rb D T 5 11 : AC AC DR : AC AC DR : AC DR : AC(0 7) INPR : AC AC : AC shr AC, AC(15) E : AC shr AC, AC(0) E : AC 0 : AC AC 1 LD CLR INR T5 D1 D2 T5 p B11 r B9 B7 B6 ADD DR INPR COM SHR SHL INC B5 CLR Fig. (5-20) B11 14

15 Adder and Logic Circuit This circuit consists of 16 single-bit adder and logic duplicated circuits. The carry output of the first stage is connected to the carry input of the next stage, and so on. INPR (1) INPR (0) DR (14) AC (15) Cin DR (14) AC (14) DR (1) AC (1) Cin DR (0) AC (0) Stage15 Stage 14 Stage 1 Stage 0 Cout Cout Cout E AC (15) AC (14) AC (1) AC (0) Detail connection of single stage 15

16 Adder and Logic circuit DR(i) AC(i) AND (Output of OR gate in Fig. 5-20) LD Ci FA ADD Ii (Fig.2-11) J Q AC(i) Ci+1 DR K bit(i) From INPR INPR COM Clock SHR AC(i+1) SHL AC(i-1) 16

17 The end of the Lecture Thanks for your time Questions are welcome 17 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU December 20, 2016

Computer Architecture and Organization:

Computer Architecture and Organization: L03: Register transfer and System Bus By: A. H. Abdul Hafez Abdul.hafez@hku.edu.tr, ah.abdulhafez@gmail.com 1 CAO, by Dr. A.H. Abdul Hafez, CE Dept. HKU Outlines