Asahi Kasei Microsystems AKM5451 Cell Phone Receiver with Interface Circuitry Circuit Analysis
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1 April 15, 2003 Asahi Kasei Microsystems AKM5451 Cell Phone Receiver with Interface Circuitry Circuit Analysis Table of Contents Introduction...Page 1 List of Figures...Page 2 Device Summary Sheet...Page 9 Schematics... Tab 1 Signal Naming Conventions and Symbol Definitions... Tab 2 Signal Cross-Reference List... Tab 3 For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks. Rev. F2.0
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3 Cell Phone Receiver with Interface Circuitry Page 2 List of Figures Package Markings Package X-Ray Pin Configuration Die Markings Die Photograph Annotated Die Photograph Die Architecture Fuse Images with Readback Annotations Metal 2, Metal 1 and Polysilicon 0.3.2a Fuse Images with Readback Annotations Metal 2 and Metal b Fuse Image with Readback Annotations Polysilicon Standard Cell Images with Readback Annotations Metal 2, Metal 1 and Polysilicon 0.3.4a VCO Images with Readback Annotations Metal 2 and Metal b VCO Image with Readback Annotations Polysilicon 0.3.5a Mixer Images with Readback Annotations Metal 2 and Metal b Mixer Image with Readback Annotations Polysilicon ESD Images with Readback Annotations Metal 2, Metal 1 and Polysilicon PNP Images with Readback Annotations Metal 2, Metal 1 and Polysilicon 0.3.8a VGA Images with Readback Annotations Metal 2 and Metal b VGA Images with Readback Annotations Polysilicon Full Adder Half Adder D Flip Flop (DFF) D Flip Flop with Set and Reset (DFFSR) D Flip Flop with Reset (DFFR1) D Flip Flop with Reset 2 (DFFR2) D Flip Flop with Reset and Inverting Option (DFFR3) Flip Flop with Active High Set (DFFS1) Flip Flop with Active Low Set (DFFS2) Rev /3/03 10:53 AM
4 Cell Phone Receiver with Interface Circuitry Page D Flip Flop with Set (DFFS3) Latch with Data Hold (Latch1) Latch with Active High Reset (Latch2) Latch with Active Low Set (Latch3) to 1 Multiplexer (MUX1) to 1 Multiplexer with Complement (MUX2) to 1 Multiplexer with Inverted Output (MUX3) Multiplexer IV Multiplexer V Multiplexer III Inverters with Clock Signals Top Level Diagram IF Mixer First IF Input Amplifier Gilbert Mixer IF Output Buffer AGC and BPF IF AGC I Variable-Gain Amplifier I Variable-Gain Amplifier II IF AGC II Variable-Gain Amplifier III Variable-Gain Amplifier IV Bias Generator BPF Stage I BPF Cell I Bias Generator BPF Stage II
5 Cell Phone Receiver with Interface Circuitry Page BPF Cell II IF Test Output RSSI Generator and RSSI LPF RSSI Preamplifier RSSI Stage I Full-Wave Rectifier I RSSI LPF I RSSI Output I RSSI Stage II Full-Wave Rectifier II RSSI LPF II RSSI Output II RSSI Current Output RSS Digitalizer I/V Amplifier A/D Amplifier Limiting Amplifier Center Frequency Adjustment Signal Generator Differential Signal Generator Low Pass Filter Bias Generator Signal Processing Amplifier Low-Pass Amplifier Signal Splitter Peak Detector Phase Measurement Differential Amplifier Full-Wave Rectifier
6 Cell Phone Receiver with Interface Circuitry Page Signal Timing Circuit Digitalizer Phase Signal Multiplier Current Generator Trimming Data Generator Fuse Data Bank Signal Selection Multiplexer Control Current Generator Decoders Programmable Current Source I Programmable Current Source II Current Generator I Current Generator II Current Generator III Current Generator IV PLL TCXO TCXO Clock Input Frequency and Phase Detector Charge Pump and LPF VCO VCO Cell Output Level Shifter Frequency Divider Clock Output Control Logic Power On Delay Circuitry {SDIN}, {STB} and {SCLK} Input Protection {SDOUT} Output Buffer Data Interface Logic
7 Cell Phone Receiver with Interface Circuitry Page Data Input Control I Bit Counter with Reset Bit Counter Data Input Logic Circuits I Data Input Logic Circuits II Bit Counter Bit Counter with Reset Bit Counter Data Input Logic Circuits III Data Input Logic Circuits IV Data Input Logic Circuits V Data Input Logic Circuits VI Data Output and Trimming Logic I Data Input Control II Serial Clock Drivers Data Output Logic Data Path Serial Data Out Trimming Control Logic II Trimming Control I Trimming Control II bit Incrementer/Decrementer Trimming Control III Register Circuit Test Data Input Circuit Trimming Control IV Trimming Control V Trimming Control Logic III Trimming Logic I
8 Cell Phone Receiver with Interface Circuitry Page Trimming Logic II Trimming Logic III Parallel to Serial Converter Parallel to Serial Converter II Parallel to Serial Converter IV Parallel to Serial Converter I IF, Mixer and PLL Control Decoder Latches I Latches II IF Stage Control Bias Circuits Bandgap Circuit Bandgap Voltage Generator Voltage Regulator Voltage Follower Reference Voltage Output Reference Current Sources I Current Sources I Current Sources II ESD Protection Circuits A.1.0 Symbol Conventions - 1 A.1.1 Symbol Conventions - 2 A.2.0 Symbol Definitions - 1 A.2.1 Symbol Definitions - 2 A.2.2 Symbol Definitions - 3 A.2.3 Symbol Definitions - 4 A.2.4 Symbol Definitions - 5 A.2.5 Symbol Definitions - 6
9 Cell Phone Receiver with Interface Circuitry Page 8 A.2.6 Symbol Definitions - 7 A.3.0 Logic Gate Size Notation A.4.0 Transistor Size Notation A.5.0 Capacitor Size Notation
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