Maxim MAX3940E Electro-Absorption Modulator Structural Analysis

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1 May 23, 2006 Maxim MAX3940E Electro-Absorption Modulator Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Some of the information in this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization's corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information.

3 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 Major Findings 2 Device Overview 2.1 Die 2.2 Die Features 3 Process 3.1 Passivation 3.2 Metallization 3.3 Intermetal Dielectrics and PMD 3.4 Vias and Contacts 3.5 MOS Transistors and Poly 3.6 Vertical NPN Heterojunction Bipolar Transistors 3.7 Lateral PNP Transistors 3.8 Diode-Like Structure 3.9 Resistors, Capacitors and Inductors 3.10 Isolation 3.11 Top Silicon Layer and Handle Wafer 4 Materials Analysis 4.1 SIMS Analysis 4.2 SRP Analysis 4.3 EDS Analysis 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions Report Evaluation

4 Overview Overview 1.1 List of Figures 2 Device Overview Annotated Die Photograph Die Markings Die Corner Die Edge Minimum Pitch Bondpads Left Bondpad Edge Right Bondpad Edge 3 Process General View of MAX3940 Process Die Edge Seal Si 3 N 4 Passivation Minimum Width Metal Minimum Pitch Metal Minimum Pitch Metal Additional Layer on Metal Minimum Pitch Metal Inter-Metal Dielectrics IMD 1 Through IMD IMD IMD IMD Pre-Metal Dielectric PMD Over Poly 2 and STI Minimum Pitch Via 3 s Via Via 2 and MIM Capacitor Minimum Pitch Via 2 s and Via 1 s Stacked Via 2 and Via Contacts to Poly Contacts to Diffusion

5 Overview NMOS Transistor Gate Poly and S/D Diffusion Double Poly Capacitor Multi-Emitter Vertical NPN Transistor Poly-Emitter Contact Vertical NPN Transistor Emitter Contact Delineated With a Glass Etch Lateral PNP Transistor N+ Base Contact Polycide Emitter Contact Silicided Collector Contact Plan-View of Diode-Like-Device Diode-Like Device Central Contact Outer Ring Contact Plan-View of the Diffusion and TiSi 2 Resistors Plan-View of Metal Film Resistors SEM Cross-Section of a Metal Film Resistor SEM Cross-Section of a Diffusion Resistor Ti Silicide Resistor Double Poly Capacitors Edge of Double Poly Capacitor MOS Capacitor Optical Plan-View of the Center Tapped Inductor SEM Cross-Section of the Inductor Poly Over STI Deep Trench Isolation

6 Overview Materials Analysis FESEM Cross-Section Through Dielectrics SIMS Profile of Dielectric Layers Pattern and Field Regions on Die Spreading Resistance Profile Through a Pattern Region Spreading Resistance Profile Through a Field Region EDS Spectrum of Metal EDS Spectrum of Metal EDS Spectrum of Metal EDS Spectrum of Metal EDS Spectrum of the Metal 2 Cap Layer EDS Spectrum of a Silicide 5 Critical Dimensions 5.1 Horizontal Dimensions 5.2 Vertical Dimensions 1.2 List of Tables Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions

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