CMOSIS CMV Mp, 5.5 µm Pixel Pitch High-Speed Pipelined Global Shutter CMOS Image Sensor with Correlated Double Sampling
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1 CMOSIS CMV Mp, 5.5 µm Pixel Pitch High-Speed Pipelined Global Shutter CMOS Image Sensor with Correlated Double Sampling Imager Process Review 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:
2 Imager Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR CYRF Revision 1.0 Published: November 23, 2011
3 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Die Utilization Analysis 3.1 Die Overview 4 Process Analysis 4.1 General Device Structure 4.2 Bond Pads 4.3 Dielectrics 4.4 Metallization and MIM Column Capacitors 4.5 Vias and Contacts 4.6 Peripheral Transistors and Poly 4.7 Isolation 4.8 Wells and Substrate 5 Pixel Analysis 5.1 Pixel Overview and Schematic 5.2 Pixel Plan-View Analysis 5.3 Pixel Cross-Sectional Analysis Parallel to Row Select Lines 5.4 Pixel Cross-Sectional Analysis Parallel to Column Out Lines
4 Imager Process Review 6 Critical Dimensions 6.1 Die and Die Feature Critical Dimensions 6.2 Die Utilization Analysis 6.3 Dielectrics 6.4 Metallization and MIM Column Capacitors 6.5 Vias and Contacts 6.6 Peripheral Transistors and Poly 6.7 Isolation 6.8 Wells and Substrate 6.9 Pixel Analysis 7 References 8 Statement of Measurement Uncertainty and Scope Variation
5 Overview Overview 1.1 List of Figures 2 Device Overview CMV4000 Package Top CMV4000 Package Planar X-Ray CMV4000 Package Bottom CMV4000 Package Side View CMV4000 Package Side-View X-Ray CMV4000 Package Detailed Side-View X-Ray CMV4000 Die Photograph Microlenses Intact CMV4000 Die Markings CMV4000 Die Photograph Microlenses Removed CMV4000 Metal 1 Die Photograph Die Corner A Die Corner A Detail Die Corner B Die Corner B Detail Die Corner C Die Corner D Die Corner D Detail Die Corner Tilt View Pixel Array Top Left Corner Pixel Array Bottom Right Corner Reference Pixels A Reference Pixels B Dummy Metal and Logic Region Interconnect Bond Pad Pitch Bond Pad Detail Microlenses Tilt View 3 Die Utilization Analysis CMV4000 Annotated Metal 1 Die Photograph 4 Process Analysis General Structure Periphery General Structure Pixel Array Die Thickness Die Edge Die Seal Bond Pad Edge TEM Overview of Passivation TEM Detail of Passivation IMD TEM of IMD IMD 2
6 Overview TEM of IMD IMD TEM of IMD PMD Peripheral Region TEM of Metal MIM Capacitor Overview TEM of MIM Capacitor Top Plate Contact TEM of MIM Capacitor Detail Metal 3 Pitch TEM of Metal TEM of Metal Metal 1 Pitch (Logic Region) TEM of Metal Via 3s Via 2s Via 1s and Contacts to Diffusion Contacts to Poly Logic Transistor Contacted Gate Pitch TEM of Logic Transistor Logic Transistor Gate Dielectric Minimum Width STI TEM of STI Poly Over STI Overview of SRP Sample SRP Bevel Location 1 (LOC.1) SRP Bevel Locations 1 and 2 (LOC.2, LOC.3) SRP of Epi and Substrate in Pixel Array (LOC.1) SRP of Peripheral N-Well (LOC.2) SRP of Peripheral P-Well (LOC.3) 5 Pixel Analysis Pixel Schematic Microlenses Plan View Pixel at Metal Pixel at Metal Pixel at Metal Pixel at Metal Pixel at Poly Pixel at Gate Dielectric Level Pixel at Diffusion and STI Planar SCM of Pixel Substrate Doping Si Surface Planar SCM of Pixel Substrate Doping Cathode Surface Pixel Overview SCM Overview of Pixel Array Edge TEM of Transfer (T1) and Reset (T2) Transistors TEM of Transfer (T1) Transistor Gate Overview
7 Overview TEM of Transfer (T1) Gate SWS Transfer Gate Dielectric TEM of Pixel Anti-Reflective Layer SCM of Transfer Gate, Pinning Layer, and N-Type Cathode Reset (T2) Transistor Gate Length Source Follower (T3) Transistor Gate Width Pre-Charge (T4) Transistor Gate Length Sample 1 (T5) Transistor Gate Width Sample 2 (T6) Transistor Gate Width Row Select (T8) Transistor Gate Length C1 Capacitor Overview TEM of C1 Capacitor Dielectric VSS Contact Edge Pixel Overview Source Follower (T3, T7) and Sample Transistor (T5, T6) Overview Source Follower (T7) Gate Length Sample 1 (T5) and Sample 2 (T6) Gate Lengths Source Follower (T3) Gate Length
8 Overview List of Tables 1 Overview Device Identification CMV4000 Device Summary CMV4000 Process Summary 2 Device Overview Die, Bond Pad, and Standard Cell Dimensions 3 Die Utilization Analysis CMV4000 Functional Block Sizes 4 Process Analysis Measured Dielectric Thicknesses Metallization and MIM Capacitor Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor and Poly Horizontal Dimensions Peripheral MOS Transistor and Poly Vertical Dimensions STI Critical Dimensions Well and Epi Thicknesses 5 Pixel Analysis Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions 6 Critical Dimensions Die, Bond Pad, and Standard Cell Dimensions CMV4000 Functional Block Sizes Measured Dielectric Thicknesses Metallization and MIM Capacitor Thicknesses Metallization Width and Pitch Via and Contact Dimensions Peripheral MOS Transistor and Poly Horizontal Dimensions Peripheral MOS Transistor and Poly Vertical Dimensions STI Critical Dimensions Well and Epi Thicknesses Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions
9 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 3685 Richmond Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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