Toshiba HEK3 0.3 Mp VGA CMOS Image Sensor 0.13 µm Toshiba Process

Transcription

1 Toshiba HEK3 0.3 Mp VGA CMOS Image Sensor 0.13 µm Toshiba Process Through Silicon Via Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Through Silicon Via Process Review Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. CWR JMRK Revision 1.0 Published: October 8, 2008 Revision 2.0 Published: November 10, 2008

3 Through Silicon Via Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Downstream Product and Package 2.2 Package Features 2.3 HEK3 CIS Die 2.4 Die Features 3 Die Front-End-of-Line (FEOL) Process 3.1 VGA CIS Die FEOL Process Overview 3.2 Device Structure 4 Through Silicon Via BEOL Process Analysis 4.1 TSV Overview 4.2 TSV Cross-Sectional Analysis 5 Critical Dimensions 5.1 Module and Die Dimensions 5.2 Observed VGA CIS Dimensions 5.3 TSV Dimensions 6 References 7 Statement of Measurement Uncertainty and Scope Variation Report Evaluation

4 Overview Overview 1.1 List of Figures 2 Device Overview Nokia 3120 Classic Cell Phone Facing Away from User Nokia 3120 Classic Cell Phone User-Facing Side Identification Markings on Nokia 3120 Classic Cell Phone Nokia 3120 Classic Cell Phone Tear Down VGA CIS Module on PCB Overview VGA CIS Module on PCB Detailed VGA CIS Module on PCB Tilt View VGA CIS Module Extracted Plan View VGA CIS Module Extracted Back View VGA CIS Module Extracted Side View VGA CIS Module Lens Removed Tilt View HEK3 CIS Assembly Plan View Minimum Pitch Solder Balls and TSV Backside of CIS Die HEK3 Assembly X-Ray Top View HEK3 Assembly X-Ray Side View HEK3 CIS Assembly Cross Section Optical HEK3 CIS Assembly Cross Section SEM HEK3 CIS Assembly Cross Section SEM Cu RDL Solder Ball SEM Solder Ball Detailed Optical Image Solder Ball Detailed SEM Image SEM EDS Spectrum of Solder Ball Die Photograph Glued to Support Glass Plate Color Filters Intact Die Photograph Color Filters Removed Die Markings Die Markings Annotated Die Photograph Die Corner A Die Corner B Die Corner C Die Corner D Die Corner A Support Glass Plates and Color Filters Removed Die Corner D Support Glass Plates and Color Filters Removed Pixel Corner Detail Minimum Pitch Test Pads

5 Overview Die Front-End-of-Line (FEOL) Process Peripheral General Structure (P2S3) Array General Structure (P1S2) Minimum Metal 1 (P1S2) Minimum Pitch Contacts to Substrate and STI (P2S3) Minimum Peripheral MOS Transistor and Contacted Gate Pitch (P2S3) Pixel Array MOS Transistor (P1S2) TEM of Oxide-Nitride-Oxide SWS Layers (P1S3) 4 Through Silicon Via BEOL Process Analysis VGA CIS Die Test Pads Connected to TSV TSV Overview Optical Plan View TSV Top Plan View TSV Bottom Plan View Minimum Pitch TSV (P1S1) Single TSV (P1S1) TSV Top (P1S1) TSV Bottom (P1S1) TEM EDS Spectrum of Cu Liner SEM EDS Spectrum of First Organic Fill SEM EDS Spectrum of Second Organic Fill TSV Bottom Left Corner SEM (P1S1) Connection to TSV Near Test Pad Right Edge (P1S1) Test Pad to Metal 1 Connection in Detail TSV Top and Cu Pedestal Corner Overview (P1S1) TEM EDS Spectrum of Oxide Liner TSV Top Corner Detail (P1S1) Oxide Liner Near TSV Corner TEM (P3S1) Oxide Liner on TSV Top Away from TSV Corner TEM (P3S1) Oxide Liner Near TSV Bottom Corner Detail (P1S1) Cu TSV Pedestal Contacting M1 Al Overview TEM (P1S1) TSV to Metal 1 Contact Detail TEM (P1S1) TEM EDS Spectrum of Al M1 Line TEM EDS Spectrum of M1 TiN Cap TEM EDS Spectrum of M1 TiN Barrier TEM EDS Spectrum of Ti Adhesion Layer

6 Overview List of Tables 1 Overview Device Identification Device Summary Summary of Major Findings 2 Device Overview Module and Die Horizontal Critical Dimensions Module and Die Vertical Critical Dimensions 3 Die Front-End-of-Line (FEOL) Process Observed VGA CIS Critical Horizontal Dimensions Observed VGA CIS Critical Vertical Dimensions Pixel Horizontal Dimensions Pixel Vertical Dimensions 4 Through Silicon Via BEOL Process Analysis TSV Critical Dimensions 5 Critical Dimensions Module and Die Horizontal Critical Dimensions Module and Die Vertical Critical Dimensions Observed VGA CIS Critical Horizontal Dimensions Observed VGA CIS Critical Vertical Dimensions Pixel Horizontal Dimensions Pixel Vertical Dimensions TSV Critical Dimensions