Freescale MRF6P3300H RF Power Field Effect Transistor Process Review
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- Laurence McKinney
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1 August 4, 2006 Freescale MRF6P3300H RF Power Field Effect Transistor Process Review For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:
2 Some of the information is this report may be covered by patents, mask and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Incorporated This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information.
3 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 MOSFET Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Passivation and Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 RF-LDMOS Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 Critical Dimensions 5 References A Apendix A: TEM and EELS Gate Oxide Analysis A.1 Addendum: Gate Oxide Analysis A.2 Transistor Dimensions Report Evaluation
4 Overview Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom Package Side Package X-Ray Side-View MRF6P3300H Package Cavity MOSFET Die MRF6P3300H MOSFET Die MOSFET Die Markings MOSFET Die Markings Capacitor Die Capacitor Die Markings Die Corner A Die Corner B Die Corner C Die Corner D MOSFET Die Tilt-View MOSFET Die Die Corner and ESD Protection Detail ESD Protection 3 Process Analysis General View of MRF6P3300H Die Thickness Die Edge Edge Seal Bond Pad Bond Pad Edge Passivation IMD PMD Minimum Width Metal Minimum Pitch Metal Tungsten Silicide Gate Shield Via Contact to Polycide Contact to Diffusion Contact to Diffusion Interface Minimum Pitch Poly Transistor Array Section Map RF-LDMOS Transistor Overview RF-LDMOS Transistor Overview SCM RF-LDMOS Transistor Drain and Source Detail of Gate SCM
5 Overview Detail of Gate RF-LDMOS Transistor Overview Source Contacts Gate Contact (Parallel to Gate) Source Contact (Parallel to Gate) Drain Contact (Parallel to Gate) ESD Protection Structure Overview Detail of Gate from ESD Protection Structure Recessed LOCOS Isolation Width Recessed LOCOS Isolation Thickness and Bird s Beak SCM of Wells and Substrate SRP Analysis Site SRP P-Well A Apendix A: TEM and EELS Gate Oxide Analysis A.1.1 TEM CMOS Gate A.1.2 TEM Gate Oxide Thickness A.1.3 STEM Image of Gate Oxide A.1.4 EELS Line Plot Gate Oxide A.1.5 STEM Image of Interface Line Profile A.1.6 EELS Line Plot Interface A.1.7 EELS Spectrum
6 Overview List of Tables 1 Overview Device Summary Process Summary 2 Device Overview Package and Die Dimensions 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Polycide Dimensions 4 Critical Dimensions Package and Die Dimensions Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor and Polycide Dimensions A Apendix A: TEM and EELS Gate Oxide Analysis A.2.1 Transistor Dimensions
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