Toshiba TH58NVG2S3BTG00 4 Gbit NAND Flash Structural Analysis
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- Angelina Wright
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1 July 5, 2005 Toshiba TH58NVG2S3BTG00 4 Gbit NAND Flash Structural Analysis For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks.
2 Table of Contents Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Device Identification 2.1 Package 2.2 Die 2.3 Die Features 3 Process Analysis 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Peripheral Low-Voltage Transistors and Poly 3.7 Peripheral High-Voltage Transistors and Poly 3.8 Flash Array Transistors and Poly 3.9 Isolation 3.10 Wells and Substrate 4 Memory Cell Analysis 4.1 Plan-View Analysis 4.2 Cross-Sectional Analysis Parallel to Bit Line 4.3 Cross-Sectional Analysis Parallel to Word Line 5 Materials Analysis 5.1 TEM-EDS Analysis
3 Table of Contents 6 Critical Dimensions 6.1 Package and Die 6.2 Horizontal Dimensions 6.3 Vertical Dimensions Report Evaluation
4 Overview Overview 1.1 List of Figures 2 Device Identification Apple ipod Shuffle A ipod Board Top Package Photograph Bottom Package Photograph Plan-View Package X-Ray Side-View Package X-Ray Die Photograph Die Markings Die Corner A Die Corner B Die Corner C Die Corner D Typical Bond Pads Minimum Pitch Bond Pads Small Bond Pad Detail Small Bond Pad Detail Between Memory Blocks Peripheral Circuitry 3 Process Analysis General Device Structure in Memory Array General Device Structure in Peripheral Area Die Edge Die Seal Structure Bond Pad Over-view Bond Pad - Edge General Dielectric Structure Passivation Passivation Nitride TEM IMD 2 and IMD IMD 1 TEM IMD, PMD and STI PMD and STI PMD TEM
5 Overview Minimum Pitch Metal Metal 3 TiN/Ti Barrier TEM Minimum Pitch Metal Minimum Pitch Metal 2 TEM Metal 2 Lengthwise TEM Metal 2 Barrier TEM Minimum Pitch Metal 1 Plan-View Metal Metal 1 TEM Metal 1 Barrier TEM Minimum Pitch Via 2s Minimum Pitch Via 1 and Contacts Minimum Pitch Contact to Polycide Via 1 TEM Self-Aligned Poly 4 Bit Line Contact Self-Aligned Poly 4 Contact TEM Self-Aligned Poly 4 Bit Line Contact Top TEM Poly 4 HVMOS Contact to Substrate Poly 4 HVMOS Contact to Substrate TEM Poly 4 HVMOS Contact to Substrate Detail Poly 4 HVMOS Contact to Substrate Bottom Peripheral NMOS Transistor Minimum Gate Length/Minimum Pitch Peripheral NMOS Transistors Minimum Gate Length Peripheral PMOS Transistor Minimum Pitch Peripheral PMOS Transistors Minimum Space Poly (Glass Etch) HVMOS Word Line Driver Transistors Plan-View HVMOS Word Line Driver Transistors Plan-View Detail HVNMOS Transistor (Glass Etch) HVMOS Transistor Detail (Glass Etch) HVMOS Transistor TEM HVMOS Transistor Detail TEM HVMOS Transistor Gate Oxide TEM Flash Memory Transistors Plan-View Floating Gate Transistors (Bit Line Cross-Section, Glass Etch) Floating Gate Transistors (Bit Line Cross-Section) TEM Floating Gate Transistors Detail (Bit Line Cross-Section) TEM
6 Overview Floating Gate Transistors ONO Inter-Poly Dielectric (Bit Line Cross-Section) TEM Floating Gate Transistors (Word Line Cross-Section) Floating Gate Transistors (Word Line Cross-Section) TEM Floating Gate Transistors ONO Inter-Poly Dielectric (Word Line Cross-Section) TEM Floating Gate Transistor Gate Oxide TEM Ground Select Transistors (Bit Line Cross-Section) Bit Line Select Transistors (Bit Line Cross-Section, Glass Etch) Bit Line Select Transistor (Bit Line Cross-Section) TEM Select Transistor Detail (Bit Line Cross-Section) TEM Gate Poly Over STI Minimum Width STI Gate Poly Over STI TEM Array Wells SCM SRP Profile of Array Well Structure SRP Profile of Periphery P-Well SRP Profile of Periphery N-Well 4 Memory Cell Analysis Annotated Die Photograph Memory Array Corner Optical Plan-View Memory Array Edge Detail Optical Plan-View Memory Array at Metal 3 (6K) Memory Array at Metal 2 Bit Lines and V SS (6K) Memory Array at Metal 2 Bit Lines, V SS and Erase Line (6K) Memory Array at Metal 2 Bit Lines Detail (60K) Memory Array at Metal 1 SSL and GSL Contacts (6K) Memory Array at Metal 1 Erase and GSL Contacts (6K) Memory Array at Metal 1 Erase and GSL Contacts (10K) Metal 1 Bit Line Local Interconnects (30K) Memory Array at Poly Word Lines (6k) Memory Array at Poly Word Lines (10k) Memory Array at Poly Word Lines SSL Contact (30k) Memory Array at Poly Word Lines GSL Contact (30k) Poly Word Lines Detail (60k) Memory Array at Poly Floating Gates Detail (60k)
7 Overview Memory Array at Substrate Edge (6K) Memory Array at Substrate (60K) Memory Array (Bit Line Cross-Section) Memory Array (Bit Line Cross-Section) Bit Line Contact and SSL Transistor (Bit Line Cross-Section) V SS Contact and GSL Transistor (Bit Line Cross-Section) Floating Gate Transistors (Bit Line Cross-Section) Erase Line Substrate Contact (Bit Line Cross-Section) Memory Array (Word Line Cross-Section) Memory Array V SS Bus Lines (Word Line Cross-Section) Bit Lines (Word Line Cross-Section) Word Lines and Floating Gate Transistors (Word Line Cross-Section) 5 Materials Analysis EDS Analysis Locations Over-View EDS Analysis Locations PMD Detail EDS Spectrum of Passivation 3 Nitride EDS Spectrum of Passivation 2 Oxide EDS Spectrum of IMD 2-2 Oxide EDS Spectrum of IMD 2-1 Oxide EDS Spectrum of IMD 1 Oxide EDS Spectrum of PMD 4 Oxide EDS Spectrum of PMD 3 Oxide EDS Spectrum of PMD-2 BPSG EDS Spectrum of Gate Cap Nitride EDS Spectrum of Poly 2 Gate Tungsten Silicide
8 Overview List of Tables Device Summary Summary of Major Process Findings Decoded TH58NVG2S3BTG00 Part Number Probable Specifications Package and Die Dimensions Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Peripheral Transistor and Polysilicon Horizontal Dimensions Peripheral Transistor and Poly Vertical Dimensions HVMOS Transistors Horizontal Dimensions HVMOS Transistors Vertical Dimensions Flash Memory Array Transistors Horizontal Dimensions Flash Memory Array Transistors Vertical Dimensions Minimum Horizontal STI Dimensions Summary of Wells Vertical Dimensions Summary of Dielectric Composition
9 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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