Powerchip Semiconductor Corporation A3R12E3GEF G6E 635BLC4M 512 Megabit DDR2 SDRAM Structural Analysis

Transcription

1 February 23, 2007 Powerchip Semiconductor Corporation A3R12E3GEF G6E 635BLC4M Structural Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Package Analysis 3.1 Package Cross Section 3.2 Stitch Bonds and Ball Bonds 3.3 BGA Solder Bumps 4 Process Analysis 4.1 General 4.2 Dielectrics 4.3 Intermetal Dielectrics 4.4 Metallization 4.5 Vias and Contacts 4.6 MOS Transistors 4.7 DRAM Cell Array Stacked Capacitors 4.8 Wells and Substrate 4.9 Fuses 5 Memory Blocks and Cells 5.1 Memory Blocks 5.2 Memory Cells 6 Material Analysis 6.1 Package 6.2 Metals and Contacts 6.3 Dielectrics 6.4 Transistor Gate Stack 6.5 Capacitor Layers

3 Structural Analysis 7 Critical Dimensions 7.1 Horizontal Dimensions 7.2 Vertical Dimensions 8 Statement of Measurement Uncertainty Report Evaluation

4 Overview Overview 1.1 List of Figures 2 Device Overview Package Top Package Bottom Die Photograph Die Markings Left Bottom Die Corner Left Top Die Corner Right Top Die Corner Right Bottom Die Corner Typical Bond Pad and Minimum Bond pad Spacing Fuse Bank Fuses 3 Package Analysis Package Plan View X-Ray Radiograph Package Cross Section SEM Image of Package Cross Section SEM Image of Die Edge Cross Section Optical Image of Stitch Bond Cross Section SEM Image of Stitch Bond Cross Section Bond Ball Cross Section Bond Pad Window Edge BGA Solder Bump Cross Section 4 Process Analysis General Structure in DRAM Array Parallel to Bitline General Structure in DRAM Array Parallel to Wordline General Structure in Peripheral Region Die Edge Seal Passivation Metal Passivation Metal 3 Sidewall Intermetal Dielectric IMD Intermetal Dielectric IMD 1 Top Layers Intermetal Dielectric IMD 1 Bottom Layers Pre-Metal Dielectric General Metallization Structure TEM Image of Metal TEM Image of Metal TEM Image of Metal 1 Bitline and Bitline Contact TEM Image of Metal 1 Layer Metal 1 Bitlines Metal 1 Lines in Periphery Region Minimum Pitch Via 2

5 Overview Deep and Shallow Via 1s Multiple Via 1s Contacts to Diffusion and to Polycide TEM Image of Contact to Diffusion Contacts to Access Transistor in DRAM Cell Array Cell Array Region Access Transistor Cell Array Region Access Transistor Gate Oxide Minimum Size Periphery Region Transistor Periphery Transistor Sidewall Spacer Periphery Transistor Gate Oxide Periphery Transistor Gate Oxide Thinning Stacked Capacitors Bottom Portion Stacked Capacitors Top Portion Stacked Capacitor Internal Layers Planar Cross Section of the Capacitors Scanning Capacitance Image of Cell Array SRP Profiling Locations Impurity Profile in Cell Array Region Impurity Profile in Periphery Region P-Well Impurity Profile in Periphery Region N-Well Fuse and Its Connections 5 Memory Blocks and Cells Capacitor Common Plates Corner of a Capacitor Common Plate Cell Array Plan View at Extension Plug Level Cell Array Plan View at Bitline Level Cell Array Plan View at Upper Poly Plug Level Cell Array Plan View at Wordline Level Cell Array Plan View at Silicon Level Cell Array Cross Section 6 Material Analysis BGA Solder Bump EDS Spectrum BGA Solder Bump and Stitch Bond Pad Bottom EDS Spectrum BGA Solder Ball Pad Top and Stitch Bond Pad Top EDS Spectrum Bond Wire and Stitch Bond Pad Plating EDS Spectrum Metal 3 Barrier EDS Spectrum Metal 2 Barrier EDS Spectrum Metal 1 EDS Spectrum Metal 1 Contact Liner EDS Spectrum Metal 1 Contact Silicide Top Passivation Layer EDS Spectrum Bottom Passivation Layer EDS Spectrum IMD 2-2 Layer EDS Spectrum IMD 2-1 Layer EDS Spectrum

6 Overview IMD1 Between Metal 2 and Capacitor Common Plate EDS Spectrum IMD 1-5 Layer EDS Spectrum IMD 1-4 Layer EDS Spectrum IMD 1-3 EDS Spectrum PMD 1-4 Layer EDS Spectrum PMD 1-2 Layer EDS Spectrum Periphery NMOS Gate Cap Top EDS Spectrum Transistor Gate Cap Bottom EDS Spectrum Transistor Gate Metal EDS Spectrum Transistor Gate Metal Pad EDS Spectrum Transistor Gate Silicide EDS Spectrum Transistor Gate Bottom Layer EDS Spectrum Capacitor Common Plate EDS Spectrum Capacitor Inside Electrode EDS Spectrum Capacitor Dielectric Layer EDS Spectrum Capacitor Outside Electrode EDS Spectrum

7 Overview List of Tables 1 Overview Package and Die Markings Process Summary Major Findings 4 Process Analysis Dielectric Composition and Thickness Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Wells and Epi Layer 7 Critical Dimensions Metals Horizontal Dimensions Vias and Contacts Horizontal Dimensions Transistors, Poly, and Isolation Vertical Dimensions

8 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com