1.3 Megapixel CMOS Image Sensor Process Review (including MN101E19A Signal Processing DSP Basic Device Analysis)

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1 October 13, 2006 Matsushita νmaicovicon MN Megapixel CMOS Image Sensor Process Review (including MN101E19A Signal Processing DSP Basic Device Analysis) For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Introduction 1.4 MN39910 Image Sensor Device Summary 1.5 MN39910 Image Sensor Process Summary 2 Package and Dice 2.1 Package 2.2 MN39910 and MN101E19A Dice 2.3 MN39910 Die Features 3 MN39910 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 Isolation 3.8 Wells and Epi 4 MN39910 Pixel Array Analysis 4.1 Pixel Schematic 4.2 Pixel Array Plan-View Analysis 4.3 Pixel Array Cross-Sectional Analysis 5 MN39910 Materials Analysis 5.1 SEM-EDS 6 MN101E19A Basic Device Analysis 6.1 MN101E19A Signal Processing DSP Device Summary 6.2 Process Rev. 2.0 May 26, 2006 IPR

3 Process Review 7 MN39910 Critical Dimensions 7.1 Package and Die 7.2 Vertical Dimensions 7.3 Horizontal Dimensions 8 References Report Evaluation Rev. 2.0 May 26, 2006 IPR

4 Overview Overview 1.1 List of Figures 2 Package and Dice NTT FOMA N900iG Cell Phone Identification Markings on NTT FOMA N900iG Cell Phone Inside the NTT FOMA N900iG Cell Phone Image Sensor Assembly Inside the NTT FOMA N900iG Cell Phone Image Sensor Assembly Top View Image Sensor Assembly Side View Image Sensor Assembly Bottom View Image Sensor Assembly Partially Disassembled Image Sensor Assembly Image Sensor Exposed Package X-Ray Side View Package X-Ray Top View Package X-Ray Detail Top View MN39910 Die Photograph MN39910 Die Markings MN101E19A Die Photograph MN101E19A Die Markings MN39910 Die Corner A MN39910 Die Corner B MN39910 Die Corner C MN39910 Minimum Pitch Bond Pads MN39910 Single Bond Pad 3 MN39910 Process General Structure Die Edge Bond Pad Bond Pad Edge Detail General Dielectric Structure Passivation ILD PMD Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Via 1 Rev 2.0 May 26, 2006 IPR

5 Overview Minimum Pitch Contacts to Polycide Contacts to Polycide and Substrate Minimum Gate Length NMOS Transistor in Pixel Array Peripheral NMOS Peripheral PMOS Minimum Width STI SRP in Pixel Array SCM Image of Pixel Array Epi and Substrate (horizontal section) SCM Image of Pixel Array P-Well in N-epi (horizontal section) Peripheral P-Well Edge 4 MN39910 Pixel Array Analysis Pixel Schematic Circuit Pixel Array Color Filters Plan-View Pixel Array at Metal 2 Plan-View Pixel Array at Metal Pixel Array and Metal Pixel Array at Poly Pixel Array at Poly Detail Pixel Array at Sunstrate SCM Image of Pixel Array at Substrate Plan-View Image of Pixel Showing Cross-Sectional Planes A to E Pixel Array General Structure (section A, top edge) Pixel Array General Structure (section A, bottom edge) Lenses and Blue and Green Color Filters (column out section) Lenses and Red-Green Color Filters (column out section) Pixel Structure Through T1 Transistor (section A) SCM Image of Pixel Through Transfer Transistor (section A) T1 Transfer Transistor Width (section A) T1 Transfer Transistor Width (section B) Pixel Array General Structure (section C) T2 Reset and T3 Source/Follower Transistor Width (section C) T2 Reset Transistor Width (section D) T3 Source/Follower Transistor Width (section E) T3 Source/Follower Transistor Width Detail (section E) Rev 2.0 May 26, 2006 IPR

6 Overview MN39910 Materials Analysis SEM Image Showing SEM-EDS Analysis Points SEM-EDS Analysis Passivation SEM-EDS Analysis of Metal 2 TiN Cap SEM-EDS Analysis of Metal 2 Al SEM-EDS Analysis of Metal 2 TiN/Ti Barrier SEM-EDS Analysis of Tungsten Contact SEM-EDS Analysis of Tungsten Contact Bottom SEM-EDS Analysis of Gate Cobalt Silicide 6 MN101E19A Basic Device Analysis General Structure Minimum Pitch Metal Minimum Gate Length NMOS Transistors 7 MN39910 Critical Dimensions 8 References 1.2 List of Tables MN39910 Image Sensor Device Summary Summary of MN39910 Major Findings νmaicovicon Package and MN39910 Die Dimensions MN39910 Dielectric Composition and Thicknesses MN39910 Metallization Thicknesses MN39910 Minimum Pitch Levels MN39910 Via and Contact Dimensions MN39910 Transistors and Polysilicon Horizontal Dimensions MN39910 Transistors and Polysilicon Vertical Dimensions MN39910 Isolation Horizontal Dimension MN39910 Wells and Epi Vertical Dimension MN39910 Pixel Horizontal Dimensions MN39910 Pixel Vertical Dimensions Transistor Dimensions in MN39910 Pixel Array MN101E19A Signal Processing DSP Device Summary MN101E19A Observed Critical Dimensions Rev 2.0 May 26, 2006 IPR

7 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com

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