PowerDsine/Freescale
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1 April 25, 2005 PowerDsine/Freescale PD Channel Power-Over-Ethernet (POE) Manager Process Review For questions, comments, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:
2 Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Major Findings 2 Package and Die 2.1 Package 2.2 Die 3 Process 3.1 General Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 MOS Transistors and Poly 3.7 LDMOS Transistors 3.8 Bipolar Transistors 3.9 Diffusion Resistors 3.10 Isolation 3.11 Wells and Epi 4 Critical Dimensions 4.1 Package and Die 4.2 Vertical Dimensions 4.3 Horizontal Dimensions 5 Report Evaluation
3 Overview 1 Overview 1.1 List of Figures 2 Package and Die NETGEAR ProSafe Switch with POE Top NETGEAR ProSafe Switch with POE Bottom NETGEAR FS108P Board PD64004 on NETGEAR FS108P Board Package Top Package Bottom Package Top with White Sticker Removed Package X-Ray Die Photograph Die Markings Die Photograph at Metal Die Photograph at Poly Die Corner a Die Corner b Die Corner c Die Corner d Minimum Pitch Bond Pads Bond Pads Bipolar Transistors Diodes and Resistors Capacitors and Bipolar Transistors Bipolar Transistors and Resistors Annotated Die Photograph 3 Process General Structure Including LDMOS Transistors Die Edge Die Seal Bond Pad Bond Pad Edge Detail General Dielectric Structure Passivation IMD IMD 2 1-1
4 Overview IMD PMD and STI PMD Detail Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Metal Minimum Pitch Via 3s Minimum Pitch Via 2s and Via 1s Minimum Pitch Contacts to Substrate Contacts to Polycide and Substrate Minimum Gate Length NMOS Transistor Minimum Space NMOS Transistors Minimum Gate Length PMOS PMOS Transistors MOS Transistors (Glass Etch Only) Minimum Pitch MOS Transistors (Glass Etch Only) LDMOS Block at Metal 1 Plan-View LDMOS Metal 1 Detail Plan-View LDMOS Poly Detail Plan-View LDMOS Transistor at Edge of Array (Length Direction) LDMOS Transistors (Length Direction) LDMOS Transistor Poly Gate (Parallel to Length Direction) LDMOS Transistor Poly Gate Contact (Parallel to Width Direction) SCM Image of LDMOS Transistor Array Edge (Length Direction) SCM Image of LDMOS Transistors Detail (Length Direction) Edge of LDMOS Array Showing DTI Ring (Length Direction) LDMOS Gate Metal Wiring Plan-View NPN Bipolar Transistors Plan-View NPN Bipolar Transistors Plan-View at Metal NPN Bipolar Transistors Plan-View at Poly NPN Bipolar Transistor SCM Image of NPN Bipolar Transistor NPN Bipolar Transistor Emitter and Base SCM Image of NPN Bipolar Transistor Emitter and Base NPN Bipolar Transistor Emitter NPN Bipolar Transistor Base and Emitter 1-2
5 Overview NPN Bipolar Transistor Base and Collector Diffusion Resistors Plan-View Diffusion Resistor Diffusion Resistor Contacts Minimum Width STI Poly over STI DTI DTI Top Detail DTI Bottom Detail SRP Analysis of P-Well SRP Analysis of N-Well SCM Image N-Well and P-Well Separated by DTI N-Well and P-Well Separated by DTI SRP Analysis in LDMOS Array 4 Critical Dimensions 5 Report Evaluation 1.2 List of Tables Device Summary Summary of Major Findings Package and Die Dimensions Dielectric Composition and Thicknesses Metallization Thicknesses Minimum Pitch Metals Via and Contact Dimensions Transistor and Polysilicon Horizontal Dimensions Transistor and Polysilicon Vertical Dimensions LDMOS Transistor Block Critical Parameters NPN Bipolar Transistor Vertical Dimensions Isolation Horizontal and Vertical Dimension Wells and Epi Vertical Dimension 1-3
6 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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