Altera 5SGXEA7K2F40C2ES Stratix V TSMC 28 nm HP Gate Last HKMG CMOS Process
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1 Altera 5SGXEA7K2F40C2ES Stratix V TSMC 28 nm HP Gate Last HKMG CMOS Process Process Review FEOL Analysis 3685 Richmond Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:
2 Process Review FEOL Analysis Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. PPR JMTW Revision 1.0 Published: October 28, 2011
3 Process Review FEOL Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profiles 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process Analysis 3.1 Analysis Locations 3.2 General Device Structure 3.3 Flip-Chip Solder Pad 3.4 Dielectrics 3.5 Isolation 3.6 Metallization 3.7 Vias and Contacts 3.8 Transistor Overview 3.9 NMOS Transistors 3.10 PMOS Transistors 3.11 Peripheral I/O Transistors 3.12 Wells and Substrate 4 Critical Dimensions 4.1 Horizontal Dimensions 4.2 Vertical Dimensions 5 References 6 Statement of Measurement Uncertainty and Scope Variation About Chipworks
4 Overview Overview 1.1 List of Figures 2 Device Overview Stratix V FPGA Package Top Stratix V FPGA Package Bottom Stratix V FPGA Package Edge Stratix V FPGA Package X-Ray Plan View SGXEA7K2F40C2ES Die Photograph Die Markings Die Corner A Die Corner B Die Corner C Die Corner D Minimum Pitch Flip-Chip Pads Flip-Chip Pad Large Inductors Small Inductors Logic NAND gate 3 Process Analysis Die Analysis Locations General Structure of 5SGXEA7K2F40C2ES Die Edge Flip-Chip Solder Bump Pad Flip-Chip Solder Bump Pad Edge Passivation SEM ILD 11, ILD 10, and ILD 9 SEM ILD 8 TEM ILD 7 SEM ILD 6 TEM ILD 5 TEM ILD 4 TEM ILD 3 TEM ILD 2 TEM ILD 1 TEM PMD TEM STI TEM Minimum Pitch Metal 12 SEM Minimum Pitch Metal 11 SEM Metal 11 Liner TEM Minimum Pitch Metal 10 and Metal 8 SEM Minimum Pitch Metal 9 TEM Metal 9 Liner TEM Minimum Pitch Metal 7 SEM Minimum Pitch Metal 6 TEM
5 Overview Minimum Pitch Metal 4 TEM Minimum Pitch Metal 3 TEM Minimum Pitch Metal 2 TEM Minimum Pitch Metal 1 TEM Metal 1 Liner TEM Minimum Pitch Via 11 SEM Minimum Pitch Via 10s, 9s, and 8s SEM Minimum Pitch Via 4 TEM Minimum Pitch Via 3 TEM Via 1 TEM Contact to NMOS Source/Drain TEM Bottom of Contact to PMOS Source/Drain TEM Contact to Gate Metal TEM Minimum NMOS Contacted Gate Pitch TEM Minimum PMOS Contacted Gate Pitch TEM Transistor Sidewall Spacer TEM NMOS Logic Transistor Overview TEM NMOS Transistor Gate Wrap TEM NMOS Gate Metals and Dielectrics TEM NMOS Gate Dielectric and Work Function Metal PMOS Logic Transistor Gate Overview TEM PMOS Transistor Gate Wrap TEM PMOS Gate Metals and Dielectrics TEM PMOS Gate Dielectric and Work Function Metal TEM N/PMOS Gate Transition Cross-Sectional TEM Isolated PMOS Transistor TEM Group of Three PMOS Transistors TEM Detail of Group of Three PMOS Transistors TEM Group of Eleven PMOS Transistors TEM SiGe Tub TEM Germanium Profile of SiGe Tub TEM-EDS Peripheral NMOS Transistor TEM Peripheral NMOS Transistor Edge TEM Peripheral NMOS Gate Dielectric and Work Function Metal TEM N-Type Dopant SIMS P-Type Dopant SIMS Logic Region SCM
6 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview Die and Bond Pad Sizes 3 Process Analysis Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Transistor Horizontal Dimensions Transistor and Silicide Vertical Dimensions Die Thickness and Well Depths 4 Critical Dimensions Die and Bond Pads Metallization Horizontal Dimensions Via and Contact Dimensions Transistor Horizontal Dimensions Dielectric Vertical Dimensions Metallization Vertical Dimensions Transistor and Silicide Vertical Dimensions Die and Well Vertical Dimensions
7 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 3685 Richmond Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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