Sony IMX118CQT 18.5 Mp, 1.25 µm Pixel Pitch Back Illuminated CIS from the Sony DSC-WX100 Camera

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1 18.5 Mp, 1.25 µm Pixel Pitch Back Illuminated CIS from the Sony DSC-WX100 Camera Imager Process Review 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7 Canada Tel:

2 Imager Process Review Some of the information in this report may be covered by patents, mask, and/or copyright protection. This report should not be taken as an inducement to infringe on these rights. Chipworks Inc all rights reserved. Chipworks and the Chipworks logo are registered trademarks of Chipworks Inc. This report is provided exclusively for the use of the purchasing organization. It can be freely copied and distributed within the purchasing organization, conditional upon the accompanying Chipworks accreditation remaining attached. Distribution of the entire report outside of the purchasing organization is strictly forbidden. The use of portions of the document for the support of the purchasing organization s corporate interest (e.g., licensing or marketing activities) is permitted, as defined by the fair use provisions of the copyright act. Accreditation to Chipworks must be attached to any portion of the reproduced information. IPR JMRK Revision 1.0 Published: March 11, 2013

3 Imager Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package Overview 2.2 Die Photograph and Die Features 3 Process Analysis 3.1 Overview 3.2 General Device Structure 3.3 Image Sensor Substrate and Wells 3.4 Image Sensor Substrate Isolation 3.5 Peripheral Transistors and Poly 3.6 Front Dielectrics 3.7 Front Metallization 3.8 Front Vias and Contacts 3.9 Wafer Bonding and Carrier Wafer 3.10 Back of Substrate Features (Dielectrics, Metals, Color Filters, and Microlenses) 3.11 Bond Pads 4 Pixel Analysis 4.1 Pixel Overview and Schematic 4.2 Pixel Plan-View Analysis 4.3 Pixel Cross-Sectional Analysis Diagonal Across FD and Transfer Gate 4.4 Pixel Cross-Sectional Analysis Parallel to Reset Lines 4.5 Pixel Cross-Sectional Analysis Parallel to CO Lines

4 Imager Process Review 5 Critical Dimensions 5.1 Die Features 5.2 Image Sensor Substrate and Wells 5.3 Image Sensor Substrate Isolation 5.4 Peripheral Transistors and Poly 5.5 Front Dielectrics 5.6 Front Metallization 5.7 Front Vias and Contacts 5.8 Wafer Bonding and Carrier Wafer 5.9 Back of Substrate Features (Dielectrics, Metals, Color Filters, and Microlenses) 5.10 Pixels 6 References 7 Statement of Measurement Uncertainty and Scope Variation About Chipworks

5 Overview Overview 1.1 List of Figures 2 Device Overview IMX118 CIS Package Front IMX118 CIS Package Back IMX118 CIS Die Removed from PWB Substrate Back IMX118 CIS Package Top X-Ray IMX118 CIS Package Side X-Ray IMX118 Back Die Photograph Annotated Back Die Photograph Die Markings Annotated Back Side Polysilicon Die Photograph Analysis Sites Die Corner A Die Corner B Die Corner C Die Corner D Active Pixel Array Corner Top Left Active Pixel Array Corner Top Right Active Pixel Array Corner Bottom Right Active Pixel Array Corner Bottom Left Pixel Array Edge with Microlens and Color Filters Intact Top Left Pixel Array Edge with Microlens and Color Filters Intact Bottom Right Detailed View of Active Pixel Array Corner Pixel Pitch Bond Pad Pitch Bond Pad Detail Test Pads Minimum Standard Logic Cell Size 3 Process Analysis General Structure Periphery General Structure Pixel Array Die Edge Right Edge Die Edge Left Edge Die Seal SIMS Analysis Sites Substrate SIMS Peripheral Region SCM of Peripheral Region Peripheral Substrate Overview Si Stain Peripheral Substrate Embedded N-Well (N-Well 1) Si Stain Substrate SIMS Pixel Array SCM of Cathodes Junction Depth SCM of Pixel Array Isolation Well and N-Type Cathodes Pixel Array Overview Si Stain DTI Overview

6 Overview DTI Top DTI Bottom Minimum Width STI Periphery Poly Over STI Periphery STI in Pixel Array SEM Poly Over STI Pixel Array Periphery MOS Transistors Oxide Etch Periphery MOS Transistors Oxide Etch Periphery NMOS Transistors Si Etch Periphery PMOS Transistors Si Etch Logic Transistor Gate TEM Logic Transistor Gate Dielectric Region TEM Logic Transistor Gate Oxide Thickness TEM Peripheral Gate Wrap and Thick Gate Dielectric PMD Overview Peripheral Region to Pixel Array Transition Pixel Array Lower PMDs TEM Pixel PMD Peripheral PMD ILD 1, ILD 2, and ILD ILD ILD IMD Passivation Minimum Pitch Metal Metal 1 TEM Minimum Pitch Metal Metal 2 Liner TEM Minimum Observed Metal 3 Pitch Minimum Pitch Metal Metal 5 SEM Minimum Pitch Contacts to Substrate, Via 1 and Via 2 in Periphery SEM Minimum Pitch Contacts to Polysilicon Periphery Contact to Pixel Transistor S/D Diffusion TEM TEM of Contact to Pixel Gate Interface Contact to Peripheral Transistor S/D Diffusion TEM Minimum Pitch Via 3s Minimum Pitch Via 4s Via Chip Carrier and Back Illuminated Substrate Overview Upper Passivation and Wafer Bond Region Carrier Wafer Bond Region TEM Back of Substrate Feature Overview TEM Overview of Back Metals, Dielectrics, Color Filters, and Microlenses Back AR Layer Overview TEM Back AR Layer HfO AR Layer Detail TEM

7 Overview Back PMD TEM Back Metal Substrate Contact Green and Red Color Filters Blue and Green Color Filters Optical Pad Color Filter Material Identification Lens and Lens Cap Size and Material Identification Bond Pad Overview Bond Pad Edge Right Edge Bond Pad Edge Left Edge Bond Pad Seal Oxide Etch 4 Pixel Analysis Shared Pixel Schematic Pixels at Metal 5 to Metal 4 Transition Pixels at Metal Pixels at Metal Pixels at Via 3/Metal Pixels at Metal Pixels at Via 2/Metal Pixels at Metal Pixels at Via 1/Metal Pixels at Metal Pixels at Poly Pixels at Diffusion Planar SCM of N-Type Cathodes Near Surface Detailed Planar SCM of N-Type Cathodes Near Surface Transfer Gate and FD Contact TEM T1 (or T4) Transfer Gate and FD Contact TEM Transfer Gate SWS Region TEM Transfer Gate and FD Contact SEM Si Stain Detailed SCM of Pixels TEM of Transfer Gate Dielectric Vertical Transistor Top Corner TEM of Transfer Gate Dielectric Vertical Transistor Bottom V pix and V SS Contacts Periphery to Dark Pixels Transition Color Filter Edge Pixel Array Edge Edge of Residual Blue Filter (Horizontal) Edge Microlens (Horizontal) Center Microlens (Horizontal) Reset, Source Follower, and Row Select Transistors Oxide Etch Reset, Source Follower, and Row Select Transistors Si Stain Pixel Array Edge Edge of Residual Blue Filter (Vertical) Edge Microlens (Vertical) Reset Transistor Gate (T5) Width Source Follower Transistor Gate (T6) Width Row Select Transistor Gate (T7) Width

8 Overview List of Tables 1 Overview Image Sensor Specifications Sony IMX118 vs. Sony CD-829 Process Technology Comparison Device Identification IMX118 Device Summary IMX118 Process Summary 2 Device Overview Die, Bond Pad, and Standard Cell Dimensions 3 Process Analysis Substrate and Well Vertical Dimensions Substrate Isolation Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Front Via and Contact Dimensions Chip Carrier Dielectric Vertical Dimensions Back Dielectrics and Metals Vertical Dimensions 4 Pixel Analysis Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions 5 Critical Dimensions Die, Bond Pad, and Standard Cell Dimensions Substrate and Well Vertical Dimensions Substrate Isolation Critical Dimensions Transistor and Poly Horizontal Dimensions Transistor and Poly Vertical Dimensions Measured Dielectric Thicknesses Front Metallization Thicknesses Front Metallization Width and Pitch Front Via and Contact Dimensions Chip Carrier Dielectric Vertical Dimensions Back Dielectrics and Metals Vertical Dimensions Pixel Horizontal Dimensions Pixel Vertical Dimensions Pixel Transistor Dimensions

9 About Chipworks About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at Chipworks 1891 Robertson Road, Suite 500 Ottawa, Ontario K2H 5B7 Canada T F Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com