Data output signals May or may not be same a input signals

Transcription

1 Combinational Logic Part 2 We ve been looking at simple combinational logic elements Gates, buffers, and drivers Now ready to go on to larger blocks MSI - Medium Scale Integration or Integrate Circuits Encapsulate standalone piece of functionality Types rithmetic circuits Data formatters and convertors Selection devices Simple communication circuits ing with MSI When we choose to use MSI parts Encapsulate a lot of functionality in small package Give up some flexibility Must use features the manufacturer has designed in Top Level View Can represent as a box Signals Input Data input signals Output Data output signals May or may not be same a input signals Control Provide timing reference Clock or strobe Selection Select From alternate input sources Different outputs / Disable or Control Timing Considerations ecause circuitry more complex Signals take longer to propagate through Must take into consider in design as whole Relationship between Control - Input Control - Output Input - Output Must be considered

2 New terms Set up time Specifies how long one signal must be Present and stable efore a second signal occurs Hold time Specifies how long a signal must remain stable fter a second signal has changed state Let s look at these graphically s with earlier measurements Made at 50% point of each signal setup hold MSI Functions Let s now look at several pieces of functionality Found in MSI circuits rithmetic rithmetic circuitry in common use in computers ddition and Subtraction ddition and subtraction relatively straight forward operations Executed much as one would expect ddition We ve looked at the basic operation of addition To implement operation in hardware Must look at truth table for full adder Must consider Two inputs and carry in Sum output and carry out Can now write 2 equations S =!!Ci +!!Ci +!!Ci + Ci Co =!Ci +!Ci +!Ci + Ci These reduce to S = Ci Co = Ci ( )+ Ci S Co Two equations give what we call full adder,, Ci Ci S Co

3 Output S, Co Consider now that we are working with 4 bit words The result of adding these two numbers Generates carry out of MS Result is too large to fit into 4 bits Have produced overflow Must be aware of this To compute 4 bit sum in hardware Can use 4 full adders from above We take the carry out from stage i Treat as carry in to stage i+1 Ci S Co Ci S Co Ci S Co Ci S Co If we examine the process of producing the 4 bit sum We observe that we cannot compute sum in column i+1 until Carry from column i is available If we define the carry propagation delay as τ carry See that for each additional column vailability of final sum delayed by τ carry For 32 bit word Total delay 32 * τ carry Which can become significant Carry Look head To get around carry delay problem Use technique called carry look ahead Idea amounts to computing carry at same time as sum Let s examine the carry out equation from above Co = Ci ( )+

4 For stage 0 we have Co 0 = Ci 0 ( 0 0 )+ 0 0 For stage 1 we have Co 1 = Ci 1 ( 1 1 )+ 1 1 Co 1 = Co 0 ( 1 1 )+ 1 1 Co 1 = (Ci 0 ( 0 0 )+ 0 0 ) ( 1 1 )+ 1 1 We can continue in the same way for each stage We can write the equation in much more compact form Consider Ci i ( i i )+ i i We call i i the generate term g i = i i i i the propagate term p i = i i Thus we have general term Co i = Ci i p i + g i Subtraction Multiplication We implement subtraction by simply using 2 s complement Can use same hardware as for addition Wallace Tree convenient scheme for fast multiplication uses parallel approach Easily implemented in combinational logic Will illustrate for 4 x 4 multiplier Use dot to indicate either 0 or 1 bit

5 The first step is to compute the partial product array Implement using ND gate array Multiply same as logical ND Reduce partial product array using collection of Full adders 3 input 2 output Within each column dd bits in groups of 3 Sum and carry bits go to next column Next level of reduction Continue to reduce until two rows remain dd remaining two rows using parallel adder Data Encoding, Decoding, and Conversion These are simply combinational logic problems We work with truth table Identify input patters Corresponding output patterns logic to do mapping Control Usually these devices Have some form of selection or enable Output enable / disable Perhaps tri state control Output Logic level, tristate, or open collector Logic level may be High true Output high when desired logical condition satisfied Low true Output low when desired logical condition satisfied Let s consider a couple of examples 3 to 1 of eight Decoder C Output = O This device O O O Has 3 data inputs O 4 Three inputs represent 8 combinations O O s reflected in 3 variable truth table O 7 8 data outputs Controls 1

6 We may also include an enable to Permit or block decoding Usually these are low true Function Map each input combination to one of 8 outputs Corresponding output to be logical 1 when is logical 0 Each output represents one of 8 bit patterns Out 0 = ~~~C With enable included each output becomes Out 0 = ~~~C~E Schematically this appears as 3 to 2 of four Data Convertor Has 3 data inputs Three inputs represent 8 combinations s reflected in 3 variable truth table 4 data outputs Controls 0 Function Each legal input combination Causes 2 of 4 output bits to be logical 1 Of the 8 possible output combinations Only 6 are legal Thus can only use 6 of input combinations Other 2 become don t cares Writing the truth table Let s draw the Karnaugh map for bit W Equation for W reduces to W = ~~C + ~~ = ~(~+~C) The others are written similarly Data Selection Data selection devices permit one to select from Several alternate data sources Usually because of pin limitations Number of choices limited to 2 Combine devices to increase number of alternatives C ~Enab C W X Y Z x x x x x x x x 0 1 C x x O 0 O 1 O 2 O 3 O 4 O 5 O 6 O 7

7 D 00 4 it Data Selector Has 8 data inputs Grouped as 2 sets of 4 4 data outputs Controls 2 Select Device Logical 0 active Selector Select one of 2 input sets Function Cause one or the other of the 2 input data sets to ppear on output When enable is logical 0 Selector = 0 Selects one group Selector = 1 Selects other group Select ~enable D 01 D 10 D 11 D 20 D 21 D 30 D 31 D 0 D 1 D 2 D 3 1 of N Data Selector - Multiplexer We can build a variation on the above device Multiplex number of data bits onto single line Has 4 data inputs 1 data output Controls 3 Select Device Logical 0 active 2 Selectors Select one of 4 input bits Function Cause one of the four input data bits to ppear on output ased upon selector pattern When enable is logical 0 D0 D1 D2 D3 Dout

8 Tristate Gates Let s take a look at another way of solving the data selection problem In our discussion of logic gates We stated Output could drive to logic 1 state or logic 0 state The output had to be in one or the other state Let s revisit our switch diagrams Vcc Vcc Vcc Output Output Output Logical 0 Logical 1 Open For the first and second configuration Output will be Logical 0 Logical 1 For the third configuration Output will be an open circuit Neither 0 nor 1 We have no connection We don t permit the fourth combination oth closed why The third configuration Represents the behaviour of a tristate gate Output may be

9 Logical 0 Logical 1 No connection - open We have four possible configurations for the tristate gate Observe that the tristate gate Has additional input called enable Function of enable input Control behaviour of output For top two gates is active low If enable is low Left hand gate cts like familiar inverter Right hand gate cts like familiar buffer If enable is high Output is open circuit For bottom two gates is active high If enable is high Left hand gate cts like familiar inverter Right hand gate cts like familiar buffer If enable is low Output is open circuit

10 4 it Data Selector Revisited Has 8 data inputs Grouped as 2 sets of 4 4 data outputs Controls 2 Select Device Logical 0 active Selector Select one of 2 input sets Function Cause one or the other of the 2 input data sets to ppear on output When enable is logical 0 Selector = 0 Selects one group Selector = 1 Selects other group D 00 D 0 D 01 D 10 D 1 D 11 D 20 D 2 D 21 D 30 D 3 D 31 Select ~enable